- Ensure context synchronisation after a write to APIAKey.

- Fix bullet list formatting in Documentation/arm64/amu.rst to eliminate
   doc warnings.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAl6jG6sACgkQa9axLQDI
 XvFFLQ/+O/AOzG7lMP/7Yoq7+5Tt3kO8CoODHc+q7nE/Kpyn58/Aa1QorzQHM3r9
 xZkEWwYZIN/XELHtfD/6m6Z6KmtgPdHN4+UT7kJi6LSy1c4ZN6CUWMBi1RrzEN1O
 VZx6n8k0EAo6utIa3ncyWlf9+F+ja84756HdZzPtI4DOWnVkZ/A2F6+XiHRSpz+o
 txjdXVRBLigJiVOHchAV9NU6dhz3O8bnUz2jAoYW0uqIVKz9z53SvN23R+w7Kqsa
 KRL38OD/gODizc92yi8YpdIpuvQIFywgHXcbFcFf6wgi9pXHiRDDL1Q1URx0op8K
 8HjM/PEcbmeBv+QN7JvrtGolqUa2IuU5EcJ/c4hbUlHLU9PoQYHZvGkdbq1aI/Xh
 x2Jv79qWu4IMyEUQeKxOs3In7TMEwNXc81q6tv3F+1e3w/T6yAl23DNSBhNZQiol
 +nZ8GUyT4Znov9VXOBXnQsj0KvzIQq7SYTE55VejmDTIiQTZMV13Rj8KEHBr5Cej
 keUx2Hyv00IHJ7kbg+Luw9DkfCXh4byWIlHb3vPQQUQSbQx4IYroblbohFx/8jAU
 mEgQSE8E7CnT82GKAWm6lIed8h9erHMr+WUtnXhVhKFaSGCljtWIdog1LbN5vGtV
 vYs/sXVnmy349NNTOLXCdIOuaUfWCDLOwagPhQwSUPJNwu4h2Q4=
 =q/zE
 -----END PGP SIGNATURE-----

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas:

 - Ensure context synchronisation after a write to APIAKey.

 - Fix bullet list formatting in Documentation/arm64/amu.rst to
   eliminate doc warnings.

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  Documentation: arm64: fix amu.rst doc warnings
  arm64: sync kernel APIAKey when installing
This commit is contained in:
Linus Torvalds 2020-04-24 11:34:43 -07:00
Родитель b9916af776 59bff30ad6
Коммит 4544db3f84
2 изменённых файлов: 32 добавлений и 24 удалений

Просмотреть файл

@ -23,13 +23,14 @@ optional external memory-mapped interface.
Version 1 of the Activity Monitors architecture implements a counter group
of four fixed and architecturally defined 64-bit event counters.
- CPU cycle counter: increments at the frequency of the CPU.
- Constant counter: increments at the fixed frequency of the system
clock.
- Instructions retired: increments with every architecturally executed
instruction.
- Memory stall cycles: counts instruction dispatch stall cycles caused by
misses in the last level cache within the clock domain.
- CPU cycle counter: increments at the frequency of the CPU.
- Constant counter: increments at the fixed frequency of the system
clock.
- Instructions retired: increments with every architecturally executed
instruction.
- Memory stall cycles: counts instruction dispatch stall cycles caused by
misses in the last level cache within the clock domain.
When in WFI or WFE these counters do not increment.
@ -57,11 +58,12 @@ counters, only the presence of the extension.
Firmware (code running at higher exception levels, e.g. arm-tf) support is
needed to:
- Enable access for lower exception levels (EL2 and EL1) to the AMU
registers.
- Enable the counters. If not enabled these will read as 0.
- Save/restore the counters before/after the CPU is being put/brought up
from the 'off' power state.
- Enable access for lower exception levels (EL2 and EL1) to the AMU
registers.
- Enable the counters. If not enabled these will read as 0.
- Save/restore the counters before/after the CPU is being put/brought up
from the 'off' power state.
When using kernels that have this feature enabled but boot with broken
firmware the user may experience panics or lockups when accessing the
@ -78,10 +80,11 @@ are not trapped in EL2/EL3.
The fixed counters of AMUv1 are accessible though the following system
register definitions:
- SYS_AMEVCNTR0_CORE_EL0
- SYS_AMEVCNTR0_CONST_EL0
- SYS_AMEVCNTR0_INST_RET_EL0
- SYS_AMEVCNTR0_MEM_STALL_EL0
- SYS_AMEVCNTR0_CORE_EL0
- SYS_AMEVCNTR0_CONST_EL0
- SYS_AMEVCNTR0_INST_RET_EL0
- SYS_AMEVCNTR0_MEM_STALL_EL0
Auxiliary platform specific counters can be accessed using
SYS_AMEVCNTR1_EL0(n), where n is a value between 0 and 15.
@ -93,9 +96,10 @@ Userspace access
----------------
Currently, access from userspace to the AMU registers is disabled due to:
- Security reasons: they might expose information about code executed in
secure mode.
- Purpose: AMU counters are intended for system management use.
- Security reasons: they might expose information about code executed in
secure mode.
- Purpose: AMU counters are intended for system management use.
Also, the presence of the feature is not visible to userspace.
@ -105,8 +109,9 @@ Virtualization
Currently, access from userspace (EL0) and kernelspace (EL1) on the KVM
guest side is disabled due to:
- Security reasons: they might expose information about code executed
by other guests or the host.
- Security reasons: they might expose information about code executed
by other guests or the host.
Any attempt to access the AMU registers will result in an UNDEFINED
exception being injected into the guest.

Просмотреть файл

@ -47,7 +47,7 @@ static inline void ptrauth_keys_init_user(struct ptrauth_keys_user *keys)
get_random_bytes(&keys->apga, sizeof(keys->apga));
}
#define __ptrauth_key_install(k, v) \
#define __ptrauth_key_install_nosync(k, v) \
do { \
struct ptrauth_key __pki_v = (v); \
write_sysreg_s(__pki_v.lo, SYS_ ## k ## KEYLO_EL1); \
@ -62,8 +62,11 @@ static __always_inline void ptrauth_keys_init_kernel(struct ptrauth_keys_kernel
static __always_inline void ptrauth_keys_switch_kernel(struct ptrauth_keys_kernel *keys)
{
if (system_supports_address_auth())
__ptrauth_key_install(APIA, keys->apia);
if (!system_supports_address_auth())
return;
__ptrauth_key_install_nosync(APIA, keys->apia);
isb();
}
extern int ptrauth_prctl_reset_keys(struct task_struct *tsk, unsigned long arg);