spi: Add Meson SPICC driver
The SPICC hardware block on the Amlogic SoCs is Communication oriented and can do Full-Duplex 8- to 32-bit width SPI transfers up to 30MHz. The current driver only supportd the PIO transfer mode since the DMA seems broken on available hardware. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Neil Armstrong
Mark Brown
Родитель
01a330da0c
Коммит
454fa271bc
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@ -393,6 +393,13 @@ config SPI_FSL_ESPI
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From MPC8536, 85xx platform uses the controller, and all P10xx,
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P20xx, P30xx,P40xx, P50xx uses this controller.
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config SPI_MESON_SPICC
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tristate "Amlogic Meson SPICC controller"
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depends on ARCH_MESON || COMPILE_TEST
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help
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This enables master mode support for the SPICC (SPI communication
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controller) available in Amlogic Meson SoCs.
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config SPI_MESON_SPIFC
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tristate "Amlogic Meson SPIFC controller"
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depends on ARCH_MESON || COMPILE_TEST
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@ -53,6 +53,7 @@ obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o
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obj-$(CONFIG_SPI_JCORE) += spi-jcore.o
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obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
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obj-$(CONFIG_SPI_LP8841_RTC) += spi-lp8841-rtc.o
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obj-$(CONFIG_SPI_MESON_SPICC) += spi-meson-spicc.o
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obj-$(CONFIG_SPI_MESON_SPIFC) += spi-meson-spifc.o
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obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
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obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
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@ -0,0 +1,619 @@
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/*
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* Driver for Amlogic Meson SPI communication controller (SPICC)
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*
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* Copyright (C) BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/reset.h>
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#include <linux/gpio.h>
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/*
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* The Meson SPICC controller could support DMA based transfers, but is not
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* implemented by the vendor code, and while having the registers documentation
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* it has never worked on the GXL Hardware.
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* The PIO mode is the only mode implemented, and due to badly designed HW :
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* - all transfers are cutted in 16 words burst because the FIFO hangs on
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* TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
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* FIFO max size chunk only
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* - CS management is dumb, and goes UP between every burst, so is really a
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* "Data Valid" signal than a Chip Select, GPIO link should be used instead
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* to have a CS go down over the full transfer
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*/
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#define SPICC_MAX_FREQ 30000000
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#define SPICC_MAX_BURST 128
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/* Register Map */
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#define SPICC_RXDATA 0x00
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#define SPICC_TXDATA 0x04
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#define SPICC_CONREG 0x08
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#define SPICC_ENABLE BIT(0)
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#define SPICC_MODE_MASTER BIT(1)
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#define SPICC_XCH BIT(2)
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#define SPICC_SMC BIT(3)
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#define SPICC_POL BIT(4)
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#define SPICC_PHA BIT(5)
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#define SPICC_SSCTL BIT(6)
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#define SPICC_SSPOL BIT(7)
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#define SPICC_DRCTL_MASK GENMASK(9, 8)
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#define SPICC_DRCTL_IGNORE 0
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#define SPICC_DRCTL_FALLING 1
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#define SPICC_DRCTL_LOWLEVEL 2
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#define SPICC_CS_MASK GENMASK(13, 12)
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#define SPICC_DATARATE_MASK GENMASK(18, 16)
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#define SPICC_DATARATE_DIV4 0
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#define SPICC_DATARATE_DIV8 1
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#define SPICC_DATARATE_DIV16 2
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#define SPICC_DATARATE_DIV32 3
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#define SPICC_BITLENGTH_MASK GENMASK(24, 19)
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#define SPICC_BURSTLENGTH_MASK GENMASK(31, 25)
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#define SPICC_INTREG 0x0c
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#define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
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#define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
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#define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
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#define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
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#define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
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#define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
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#define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
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#define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */
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#define SPICC_DMAREG 0x10
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#define SPICC_DMA_ENABLE BIT(0)
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#define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1)
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#define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6)
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#define SPICC_READ_BURST_MASK GENMASK(14, 11)
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#define SPICC_WRITE_BURST_MASK GENMASK(18, 15)
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#define SPICC_DMA_URGENT BIT(19)
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#define SPICC_DMA_THREADID_MASK GENMASK(25, 20)
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#define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26)
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#define SPICC_STATREG 0x14
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#define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */
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#define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
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#define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */
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#define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */
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#define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
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#define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */
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#define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */
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#define SPICC_TC BIT(7) /* Transfert Complete Interrupt */
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#define SPICC_PERIODREG 0x18
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#define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */
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#define SPICC_TESTREG 0x1c
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#define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */
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#define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */
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#define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */
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#define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
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#define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */
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#define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */
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#define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */
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#define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */
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#define SPICC_DLYCTL_W1_MASK GENMASK(21, 16) /* Delay Control Write-Only */
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#define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */
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#define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */
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#define SPICC_DRADDR 0x20 /* Read Address of DMA */
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#define SPICC_DWADDR 0x24 /* Write Address of DMA */
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#define writel_bits_relaxed(mask, val, addr) \
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writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
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#define SPICC_BURST_MAX 16
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#define SPICC_FIFO_HALF 10
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struct meson_spicc_device {
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struct spi_master *master;
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struct platform_device *pdev;
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void __iomem *base;
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struct clk *core;
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struct spi_message *message;
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struct spi_transfer *xfer;
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u8 *tx_buf;
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u8 *rx_buf;
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unsigned int bytes_per_word;
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unsigned long tx_remain;
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unsigned long txb_remain;
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unsigned long rx_remain;
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unsigned long rxb_remain;
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unsigned long xfer_remain;
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bool is_burst_end;
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bool is_last_burst;
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};
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static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
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{
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return !!FIELD_GET(SPICC_TF,
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readl_relaxed(spicc->base + SPICC_STATREG));
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}
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static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
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{
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return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF_EN,
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readl_relaxed(spicc->base + SPICC_STATREG));
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}
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static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
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{
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unsigned int bytes = spicc->bytes_per_word;
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unsigned int byte_shift = 0;
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u32 data = 0;
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u8 byte;
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while (bytes--) {
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byte = *spicc->tx_buf++;
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data |= (byte & 0xff) << byte_shift;
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byte_shift += 8;
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}
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spicc->tx_remain--;
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return data;
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}
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static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
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u32 data)
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{
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unsigned int bytes = spicc->bytes_per_word;
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unsigned int byte_shift = 0;
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u8 byte;
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while (bytes--) {
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byte = (data >> byte_shift) & 0xff;
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*spicc->rx_buf++ = byte;
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byte_shift += 8;
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}
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spicc->rx_remain--;
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}
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static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
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{
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/* Empty RX FIFO */
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while (spicc->rx_remain &&
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meson_spicc_rxready(spicc))
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meson_spicc_push_data(spicc,
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readl_relaxed(spicc->base + SPICC_RXDATA));
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}
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static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
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{
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/* Fill Up TX FIFO */
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while (spicc->tx_remain &&
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!meson_spicc_txfull(spicc))
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writel_relaxed(meson_spicc_pull_data(spicc),
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spicc->base + SPICC_TXDATA);
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}
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static inline u32 meson_spicc_setup_rx_irq(struct meson_spicc_device *spicc,
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u32 irq_ctrl)
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{
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if (spicc->rx_remain > SPICC_FIFO_HALF)
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irq_ctrl |= SPICC_RH_EN;
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else
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irq_ctrl |= SPICC_RR_EN;
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return irq_ctrl;
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}
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static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc,
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unsigned int burst_len)
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{
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/* Setup Xfer variables */
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spicc->tx_remain = burst_len;
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spicc->rx_remain = burst_len;
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spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
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spicc->is_burst_end = false;
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if (burst_len < SPICC_BURST_MAX || !spicc->xfer_remain)
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spicc->is_last_burst = true;
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else
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spicc->is_last_burst = false;
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/* Setup burst length */
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writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
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FIELD_PREP(SPICC_BURSTLENGTH_MASK,
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burst_len),
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spicc->base + SPICC_CONREG);
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/* Fill TX FIFO */
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meson_spicc_tx(spicc);
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}
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static irqreturn_t meson_spicc_irq(int irq, void *data)
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{
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struct meson_spicc_device *spicc = (void *) data;
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u32 ctrl = readl_relaxed(spicc->base + SPICC_INTREG);
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u32 stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl;
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ctrl &= ~(SPICC_RH_EN | SPICC_RR_EN);
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/* Empty RX FIFO */
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meson_spicc_rx(spicc);
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/* Enable TC interrupt since we transferred everything */
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if (!spicc->tx_remain && !spicc->rx_remain) {
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spicc->is_burst_end = true;
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/* Enable TC interrupt */
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ctrl |= SPICC_TC_EN;
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/* Reload IRQ status */
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stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl;
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}
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/* Check transfer complete */
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if ((stat & SPICC_TC) && spicc->is_burst_end) {
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unsigned int burst_len;
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/* Clear TC bit */
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writel_relaxed(SPICC_TC, spicc->base + SPICC_STATREG);
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/* Disable TC interrupt */
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ctrl &= ~SPICC_TC_EN;
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if (spicc->is_last_burst) {
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/* Disable all IRQs */
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writel(0, spicc->base + SPICC_INTREG);
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spi_finalize_current_transfer(spicc->master);
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return IRQ_HANDLED;
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}
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burst_len = min_t(unsigned int,
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spicc->xfer_remain / spicc->bytes_per_word,
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SPICC_BURST_MAX);
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/* Setup burst */
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meson_spicc_setup_burst(spicc, burst_len);
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/* Restart burst */
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writel_bits_relaxed(SPICC_XCH, SPICC_XCH,
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spicc->base + SPICC_CONREG);
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}
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/* Setup RX interrupt trigger */
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ctrl = meson_spicc_setup_rx_irq(spicc, ctrl);
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/* Reconfigure interrupts */
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writel(ctrl, spicc->base + SPICC_INTREG);
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return IRQ_HANDLED;
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}
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static u32 meson_spicc_setup_speed(struct meson_spicc_device *spicc, u32 conf,
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u32 speed)
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{
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unsigned long parent, value;
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unsigned int i, div;
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parent = clk_get_rate(spicc->core);
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/* Find closest inferior/equal possible speed */
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for (i = 0 ; i < 7 ; ++i) {
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/* 2^(data_rate+2) */
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value = parent >> (i + 2);
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if (value <= speed)
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break;
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}
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/* If provided speed it lower than max divider, use max divider */
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if (i > 7) {
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div = 7;
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dev_warn_once(&spicc->pdev->dev, "unable to get close to speed %u\n",
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speed);
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} else
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div = i;
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dev_dbg(&spicc->pdev->dev, "parent %lu, speed %u -> %lu (%u)\n",
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parent, speed, value, div);
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conf &= ~SPICC_DATARATE_MASK;
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conf |= FIELD_PREP(SPICC_DATARATE_MASK, div);
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return conf;
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}
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static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
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struct spi_transfer *xfer)
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{
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u32 conf, conf_orig;
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/* Read original configuration */
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conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
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/* Select closest divider */
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conf = meson_spicc_setup_speed(spicc, conf, xfer->speed_hz);
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/* Setup word width */
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conf &= ~SPICC_BITLENGTH_MASK;
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conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
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(spicc->bytes_per_word << 3) - 1);
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/* Ignore if unchanged */
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if (conf != conf_orig)
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writel_relaxed(conf, spicc->base + SPICC_CONREG);
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}
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static int meson_spicc_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct meson_spicc_device *spicc = spi_master_get_devdata(master);
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unsigned int burst_len;
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u32 irq = 0;
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/* Store current transfer */
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spicc->xfer = xfer;
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/* Setup transfer parameters */
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spicc->tx_buf = (u8 *)xfer->tx_buf;
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spicc->rx_buf = (u8 *)xfer->rx_buf;
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spicc->xfer_remain = xfer->len;
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/* Pre-calculate word size */
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spicc->bytes_per_word =
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DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
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/* Setup transfer parameters */
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meson_spicc_setup_xfer(spicc, xfer);
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burst_len = min_t(unsigned int,
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spicc->xfer_remain / spicc->bytes_per_word,
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SPICC_BURST_MAX);
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meson_spicc_setup_burst(spicc, burst_len);
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irq = meson_spicc_setup_rx_irq(spicc, irq);
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/* Start burst */
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writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
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/* Enable interrupts */
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writel_relaxed(irq, spicc->base + SPICC_INTREG);
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return 1;
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}
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static int meson_spicc_prepare_message(struct spi_master *master,
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struct spi_message *message)
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{
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struct meson_spicc_device *spicc = spi_master_get_devdata(master);
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struct spi_device *spi = message->spi;
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u32 conf = 0;
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/* Store current message */
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spicc->message = message;
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/* Enable Master */
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conf |= SPICC_ENABLE;
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conf |= SPICC_MODE_MASTER;
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/* SMC = 0 */
|
||||
|
||||
/* Setup transfer mode */
|
||||
if (spi->mode & SPI_CPOL)
|
||||
conf |= SPICC_POL;
|
||||
else
|
||||
conf &= ~SPICC_POL;
|
||||
|
||||
if (spi->mode & SPI_CPHA)
|
||||
conf |= SPICC_PHA;
|
||||
else
|
||||
conf &= ~SPICC_PHA;
|
||||
|
||||
/* SSCTL = 0 */
|
||||
|
||||
if (spi->mode & SPI_CS_HIGH)
|
||||
conf |= SPICC_SSPOL;
|
||||
else
|
||||
conf &= ~SPICC_SSPOL;
|
||||
|
||||
if (spi->mode & SPI_READY)
|
||||
conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
|
||||
else
|
||||
conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
|
||||
|
||||
/* Select CS */
|
||||
conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
|
||||
|
||||
/* Default Clock rate core/4 */
|
||||
|
||||
/* Default 8bit word */
|
||||
conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
|
||||
|
||||
writel_relaxed(conf, spicc->base + SPICC_CONREG);
|
||||
|
||||
/* Setup no wait cycles by default */
|
||||
writel_relaxed(0, spicc->base + SPICC_PERIODREG);
|
||||
|
||||
writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_spicc_unprepare_transfer(struct spi_master *master)
|
||||
{
|
||||
struct meson_spicc_device *spicc = spi_master_get_devdata(master);
|
||||
|
||||
/* Disable all IRQs */
|
||||
writel(0, spicc->base + SPICC_INTREG);
|
||||
|
||||
/* Disable controller */
|
||||
writel_bits_relaxed(SPICC_ENABLE, 0, spicc->base + SPICC_CONREG);
|
||||
|
||||
device_reset_optional(&spicc->pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_spicc_setup(struct spi_device *spi)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (!spi->controller_state)
|
||||
spi->controller_state = spi_master_get_devdata(spi->master);
|
||||
else if (gpio_is_valid(spi->cs_gpio))
|
||||
goto out_gpio;
|
||||
else if (spi->cs_gpio == -ENOENT)
|
||||
return 0;
|
||||
|
||||
if (gpio_is_valid(spi->cs_gpio)) {
|
||||
ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
|
||||
if (ret) {
|
||||
dev_err(&spi->dev, "failed to request cs gpio\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
out_gpio:
|
||||
ret = gpio_direction_output(spi->cs_gpio,
|
||||
!(spi->mode & SPI_CS_HIGH));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void meson_spicc_cleanup(struct spi_device *spi)
|
||||
{
|
||||
if (gpio_is_valid(spi->cs_gpio))
|
||||
gpio_free(spi->cs_gpio);
|
||||
|
||||
spi->controller_state = NULL;
|
||||
}
|
||||
|
||||
static int meson_spicc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct meson_spicc_device *spicc;
|
||||
struct resource *res;
|
||||
int ret, irq, rate;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
|
||||
if (!master) {
|
||||
dev_err(&pdev->dev, "master allocation failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
spicc = spi_master_get_devdata(master);
|
||||
spicc->master = master;
|
||||
|
||||
spicc->pdev = pdev;
|
||||
platform_set_drvdata(pdev, spicc);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
spicc->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(spicc->base)) {
|
||||
dev_err(&pdev->dev, "io resource mapping failed\n");
|
||||
ret = PTR_ERR(spicc->base);
|
||||
goto out_master;
|
||||
}
|
||||
|
||||
/* Disable all IRQs */
|
||||
writel_relaxed(0, spicc->base + SPICC_INTREG);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
|
||||
0, NULL, spicc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "irq request failed\n");
|
||||
goto out_master;
|
||||
}
|
||||
|
||||
spicc->core = devm_clk_get(&pdev->dev, "core");
|
||||
if (IS_ERR(spicc->core)) {
|
||||
dev_err(&pdev->dev, "core clock request failed\n");
|
||||
ret = PTR_ERR(spicc->core);
|
||||
goto out_master;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(spicc->core);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "core clock enable failed\n");
|
||||
goto out_master;
|
||||
}
|
||||
rate = clk_get_rate(spicc->core);
|
||||
|
||||
device_reset_optional(&pdev->dev);
|
||||
|
||||
master->num_chipselect = 4;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(32) |
|
||||
SPI_BPW_MASK(24) |
|
||||
SPI_BPW_MASK(16) |
|
||||
SPI_BPW_MASK(8);
|
||||
master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
|
||||
master->min_speed_hz = rate >> 9;
|
||||
master->setup = meson_spicc_setup;
|
||||
master->cleanup = meson_spicc_cleanup;
|
||||
master->prepare_message = meson_spicc_prepare_message;
|
||||
master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
|
||||
master->transfer_one = meson_spicc_transfer_one;
|
||||
|
||||
/* Setup max rate according to the Meson GX datasheet */
|
||||
if ((rate >> 2) > SPICC_MAX_FREQ)
|
||||
master->max_speed_hz = SPICC_MAX_FREQ;
|
||||
else
|
||||
master->max_speed_hz = rate >> 2;
|
||||
|
||||
ret = devm_spi_register_master(&pdev->dev, master);
|
||||
if (!ret)
|
||||
return 0;
|
||||
|
||||
dev_err(&pdev->dev, "spi master registration failed\n");
|
||||
|
||||
out_master:
|
||||
spi_master_put(master);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int meson_spicc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
|
||||
|
||||
/* Disable SPI */
|
||||
writel(0, spicc->base + SPICC_CONREG);
|
||||
|
||||
clk_disable_unprepare(spicc->core);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id meson_spicc_of_match[] = {
|
||||
{ .compatible = "amlogic,meson-gx-spicc", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
|
||||
|
||||
static struct platform_driver meson_spicc_driver = {
|
||||
.probe = meson_spicc_probe,
|
||||
.remove = meson_spicc_remove,
|
||||
.driver = {
|
||||
.name = "meson-spicc",
|
||||
.of_match_table = of_match_ptr(meson_spicc_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(meson_spicc_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
|
||||
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
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