rapidio/tsi721_dma: fix hardware error handling
Add DMA channel re-initialization after an error to avoid termination of all pending transfer requests. Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com> Reported-by: Barry Wood <barry.wood@idt.com> Tested-by: Barry Wood <barry.wood@idt.com> Cc: Matt Porter <mporter@kernel.crashing.org> Cc: Aurelien Jacquiot <a-jacquiot@ti.com> Cc: Andre van Herk <andre.van.herk@prodrive-technologies.com> Cc: Barry Wood <barry.wood@idt.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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458bdf6e39
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@ -282,7 +282,7 @@ void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan)
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/* Disable BDMA channel interrupts */
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iowrite32(0, bdma_chan->regs + TSI721_DMAC_INTE);
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if (bdma_chan->active)
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tasklet_schedule(&bdma_chan->tasklet);
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tasklet_hi_schedule(&bdma_chan->tasklet);
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}
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#ifdef CONFIG_PCI_MSI
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@ -298,7 +298,7 @@ static irqreturn_t tsi721_bdma_msix(int irq, void *ptr)
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struct tsi721_bdma_chan *bdma_chan = ptr;
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if (bdma_chan->active)
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tasklet_schedule(&bdma_chan->tasklet);
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tasklet_hi_schedule(&bdma_chan->tasklet);
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return IRQ_HANDLED;
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}
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#endif /* CONFIG_PCI_MSI */
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@ -584,13 +584,71 @@ static void tsi721_dma_tasklet(unsigned long data)
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iowrite32(dmac_int, bdma_chan->regs + TSI721_DMAC_INT);
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if (dmac_int & TSI721_DMAC_INT_ERR) {
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int i = 10000;
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struct tsi721_tx_desc *desc;
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desc = bdma_chan->active_tx;
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dmac_sts = ioread32(bdma_chan->regs + TSI721_DMAC_STS);
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tsi_err(&bdma_chan->dchan.dev->device,
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"ERR - DMAC%d_STS = 0x%x",
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bdma_chan->id, dmac_sts);
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"DMAC%d_STS = 0x%x did=%d raddr=0x%llx",
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bdma_chan->id, dmac_sts, desc->destid, desc->rio_addr);
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/* Re-initialize DMA channel if possible */
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if ((dmac_sts & TSI721_DMAC_STS_ABORT) == 0)
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goto err_out;
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tsi721_clr_stat(bdma_chan);
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spin_lock(&bdma_chan->lock);
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/* Put DMA channel into init state */
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iowrite32(TSI721_DMAC_CTL_INIT,
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bdma_chan->regs + TSI721_DMAC_CTL);
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do {
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udelay(1);
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dmac_sts = ioread32(bdma_chan->regs + TSI721_DMAC_STS);
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i--;
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} while ((dmac_sts & TSI721_DMAC_STS_ABORT) && i);
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if (dmac_sts & TSI721_DMAC_STS_ABORT) {
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tsi_err(&bdma_chan->dchan.dev->device,
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"Failed to re-initiate DMAC%d", bdma_chan->id);
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spin_unlock(&bdma_chan->lock);
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goto err_out;
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}
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/* Setup DMA descriptor pointers */
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iowrite32(((u64)bdma_chan->bd_phys >> 32),
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bdma_chan->regs + TSI721_DMAC_DPTRH);
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iowrite32(((u64)bdma_chan->bd_phys & TSI721_DMAC_DPTRL_MASK),
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bdma_chan->regs + TSI721_DMAC_DPTRL);
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/* Setup descriptor status FIFO */
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iowrite32(((u64)bdma_chan->sts_phys >> 32),
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bdma_chan->regs + TSI721_DMAC_DSBH);
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iowrite32(((u64)bdma_chan->sts_phys & TSI721_DMAC_DSBL_MASK),
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bdma_chan->regs + TSI721_DMAC_DSBL);
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iowrite32(TSI721_DMAC_DSSZ_SIZE(bdma_chan->sts_size),
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bdma_chan->regs + TSI721_DMAC_DSSZ);
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/* Clear interrupt bits */
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iowrite32(TSI721_DMAC_INT_ALL,
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bdma_chan->regs + TSI721_DMAC_INT);
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ioread32(bdma_chan->regs + TSI721_DMAC_INT);
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bdma_chan->wr_count = bdma_chan->wr_count_next = 0;
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bdma_chan->sts_rdptr = 0;
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udelay(10);
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desc = bdma_chan->active_tx;
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desc->status = DMA_ERROR;
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dma_cookie_complete(&desc->txd);
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list_add(&desc->desc_node, &bdma_chan->free_list);
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bdma_chan->active_tx = NULL;
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if (bdma_chan->active)
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tsi721_advance_work(bdma_chan, NULL);
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spin_unlock(&bdma_chan->lock);
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}
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@ -619,16 +677,19 @@ static void tsi721_dma_tasklet(unsigned long data)
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}
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list_add(&desc->desc_node, &bdma_chan->free_list);
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bdma_chan->active_tx = NULL;
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tsi721_advance_work(bdma_chan, NULL);
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if (bdma_chan->active)
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tsi721_advance_work(bdma_chan, NULL);
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spin_unlock(&bdma_chan->lock);
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if (callback)
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callback(param);
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} else {
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tsi721_advance_work(bdma_chan, bdma_chan->active_tx);
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if (bdma_chan->active)
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tsi721_advance_work(bdma_chan,
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bdma_chan->active_tx);
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spin_unlock(&bdma_chan->lock);
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}
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}
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err_out:
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/* Re-Enable BDMA channel interrupts */
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iowrite32(TSI721_DMAC_INT_ALL, bdma_chan->regs + TSI721_DMAC_INTE);
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}
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@ -841,7 +902,6 @@ static int tsi721_terminate_all(struct dma_chan *dchan)
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{
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struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
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struct tsi721_tx_desc *desc, *_d;
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u32 dmac_int;
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LIST_HEAD(list);
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tsi_debug(DMA, &dchan->dev->device, "DMAC%d", bdma_chan->id);
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@ -850,7 +910,10 @@ static int tsi721_terminate_all(struct dma_chan *dchan)
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bdma_chan->active = false;
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if (!tsi721_dma_is_idle(bdma_chan)) {
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while (!tsi721_dma_is_idle(bdma_chan)) {
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udelay(5);
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#if (0)
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/* make sure to stop the transfer */
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iowrite32(TSI721_DMAC_CTL_SUSP,
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bdma_chan->regs + TSI721_DMAC_CTL);
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@ -859,6 +922,7 @@ static int tsi721_terminate_all(struct dma_chan *dchan)
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do {
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dmac_int = ioread32(bdma_chan->regs + TSI721_DMAC_INT);
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} while ((dmac_int & TSI721_DMAC_INT_SUSP) == 0);
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#endif
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}
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if (bdma_chan->active_tx)
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