Add non-Virtex5 support for LL TEMAC driver
This patch adds support for using the LL TEMAC Ethernet driver on non-Virtex 5 platforms by adding support for accessing the Soft DMA registers as if they were memory mapped instead of solely through the DCR's (available on the Virtex 5). The patch also updates the driver so that it runs on the MicroBlaze. The changes were tested on the PowerPC 440, PowerPC 405, and the MicroBlaze platforms. Signed-off-by: John Tyner <jtyner@cs.ucr.edu> Signed-off-by: John Linn <john.linn@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
John Linn
David S. Miller
Родитель
3a7f8681ff
Коммит
4595691455
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@ -12,6 +12,7 @@
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#include <asm/registers.h>
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#include <asm/setup.h>
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#include <asm/irqflags.h>
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#include <asm/cache.h>
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#include <asm-generic/cmpxchg.h>
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#include <asm-generic/cmpxchg-local.h>
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@ -93,4 +94,14 @@ extern struct dentry *of_debugfs_root;
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#define arch_align_stack(x) (x)
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/*
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* MicroBlaze doesn't handle unaligned accesses in hardware.
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*
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* Based on this we force the IP header alignment in network drivers.
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* We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
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* cacheline alignment of buffers.
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*/
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#define NET_IP_ALIGN 2
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#define NET_SKB_PAD L1_CACHE_BYTES
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#endif /* _ASM_MICROBLAZE_SYSTEM_H */
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@ -2435,8 +2435,8 @@ config MV643XX_ETH
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config XILINX_LL_TEMAC
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tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver"
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depends on PPC || MICROBLAZE
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select PHYLIB
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depends on PPC_DCR_NATIVE
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help
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This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
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core used in Xilinx Spartan and Virtex FPGAs
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@ -5,8 +5,11 @@
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#include <linux/netdevice.h>
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#include <linux/of.h>
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#include <linux/spinlock.h>
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#ifdef CONFIG_PPC_DCR
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#include <asm/dcr.h>
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#include <asm/dcr-regs.h>
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#endif
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/* packet size info */
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#define XTE_HDR_SIZE 14 /* size of Ethernet header */
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@ -290,9 +293,6 @@ This option defaults to enabled (set) */
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#define TX_CONTROL_CALC_CSUM_MASK 1
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#define XTE_ALIGN 32
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#define BUFFER_ALIGN(adr) ((XTE_ALIGN - ((u32) adr)) % XTE_ALIGN)
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#define MULTICAST_CAM_TABLE_NUM 4
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/* TX/RX CURDESC_PTR points to first descriptor */
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@ -335,9 +335,15 @@ struct temac_local {
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struct mii_bus *mii_bus; /* MII bus reference */
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int mdio_irqs[PHY_MAX_ADDR]; /* IRQs table for MDIO bus */
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/* IO registers and IRQs */
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/* IO registers, dma functions and IRQs */
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void __iomem *regs;
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void __iomem *sdma_regs;
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#ifdef CONFIG_PPC_DCR
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dcr_host_t sdma_dcrs;
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#endif
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u32 (*dma_in)(struct temac_local *, int);
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void (*dma_out)(struct temac_local *, int, u32);
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int tx_irq;
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int rx_irq;
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int emac_num;
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@ -20,9 +20,6 @@
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* or rx, so this should be okay.
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*
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* TODO:
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* - Fix driver to work on more than just Virtex5. Right now the driver
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* assumes that the locallink DMA registers are accessed via DCR
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* instructions.
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* - Factor out locallink DMA code into separate driver
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* - Fix multicast assignment.
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* - Fix support for hardware checksumming.
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@ -115,16 +112,85 @@ void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
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temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
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}
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/**
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* temac_dma_in32 - Memory mapped DMA read, this function expects a
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* register input that is based on DCR word addresses which
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* are then converted to memory mapped byte addresses
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*/
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static u32 temac_dma_in32(struct temac_local *lp, int reg)
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{
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return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
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}
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/**
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* temac_dma_out32 - Memory mapped DMA read, this function expects a
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* register input that is based on DCR word addresses which
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* are then converted to memory mapped byte addresses
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*/
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static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
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{
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out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
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}
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/* DMA register access functions can be DCR based or memory mapped.
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* The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
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* memory mapped.
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*/
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#ifdef CONFIG_PPC_DCR
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/**
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* temac_dma_dcr_in32 - DCR based DMA read
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*/
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static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
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{
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return dcr_read(lp->sdma_dcrs, reg);
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}
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static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
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/**
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* temac_dma_dcr_out32 - DCR based DMA write
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*/
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static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
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{
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dcr_write(lp->sdma_dcrs, reg, value);
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}
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/**
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* temac_dcr_setup - If the DMA is DCR based, then setup the address and
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* I/O functions
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*/
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static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
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struct device_node *np)
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{
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unsigned int dcrs;
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/* setup the dcr address mapping if it's in the device tree */
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dcrs = dcr_resource_start(np, 0);
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if (dcrs != 0) {
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lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
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lp->dma_in = temac_dma_dcr_in;
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lp->dma_out = temac_dma_dcr_out;
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dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
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return 0;
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}
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/* no DCR in the device tree, indicate a failure */
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return -1;
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}
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#else
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/*
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* temac_dcr_setup - This is a stub for when DCR is not supported,
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* such as with MicroBlaze
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*/
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static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
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struct device_node *np)
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{
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return -1;
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}
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#endif
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/**
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* temac_dma_bd_init - Setup buffer descriptor rings
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*/
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@ -155,14 +221,14 @@ static int temac_dma_bd_init(struct net_device *ndev)
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lp->rx_bd_v[i].next = lp->rx_bd_p +
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sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
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skb = alloc_skb(XTE_MAX_JUMBO_FRAME_SIZE
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+ XTE_ALIGN, GFP_ATOMIC);
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skb = netdev_alloc_skb_ip_align(ndev,
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XTE_MAX_JUMBO_FRAME_SIZE);
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if (skb == 0) {
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dev_err(&ndev->dev, "alloc_skb error %d\n", i);
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return -1;
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}
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lp->rx_skb[i] = skb;
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skb_reserve(skb, BUFFER_ALIGN(skb->data));
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/* returns physical address of skb->data */
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lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
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skb->data,
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@ -172,23 +238,23 @@ static int temac_dma_bd_init(struct net_device *ndev)
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lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
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}
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temac_dma_out32(lp, TX_CHNL_CTRL, 0x10220400 |
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lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
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CHNL_CTRL_IRQ_EN |
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CHNL_CTRL_IRQ_DLY_EN |
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CHNL_CTRL_IRQ_COAL_EN);
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/* 0x10220483 */
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/* 0x00100483 */
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temac_dma_out32(lp, RX_CHNL_CTRL, 0xff010000 |
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lp->dma_out(lp, RX_CHNL_CTRL, 0xff010000 |
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CHNL_CTRL_IRQ_EN |
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CHNL_CTRL_IRQ_DLY_EN |
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CHNL_CTRL_IRQ_COAL_EN |
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CHNL_CTRL_IRQ_IOE);
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/* 0xff010283 */
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temac_dma_out32(lp, RX_CURDESC_PTR, lp->rx_bd_p);
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temac_dma_out32(lp, RX_TAILDESC_PTR,
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lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
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lp->dma_out(lp, RX_TAILDESC_PTR,
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lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
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temac_dma_out32(lp, TX_CURDESC_PTR, lp->tx_bd_p);
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lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
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return 0;
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}
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@ -426,9 +492,9 @@ static void temac_device_reset(struct net_device *ndev)
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temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
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/* Reset Local Link (DMA) */
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temac_dma_out32(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
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lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
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timeout = 1000;
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while (temac_dma_in32(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
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while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
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udelay(1);
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if (--timeout == 0) {
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dev_err(&ndev->dev,
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@ -436,7 +502,7 @@ static void temac_device_reset(struct net_device *ndev)
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break;
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}
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}
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temac_dma_out32(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
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lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
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temac_dma_bd_init(ndev);
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@ -597,7 +663,7 @@ static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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lp->tx_bd_tail = 0;
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/* Kick off the transfer */
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temac_dma_out32(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
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lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
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return NETDEV_TX_OK;
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}
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@ -639,16 +705,15 @@ static void ll_temac_recv(struct net_device *ndev)
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ndev->stats.rx_packets++;
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ndev->stats.rx_bytes += length;
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new_skb = alloc_skb(XTE_MAX_JUMBO_FRAME_SIZE + XTE_ALIGN,
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GFP_ATOMIC);
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new_skb = netdev_alloc_skb_ip_align(ndev,
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XTE_MAX_JUMBO_FRAME_SIZE);
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if (new_skb == 0) {
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dev_err(&ndev->dev, "no memory for new sk_buff\n");
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spin_unlock_irqrestore(&lp->rx_lock, flags);
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return;
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}
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skb_reserve(new_skb, BUFFER_ALIGN(new_skb->data));
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cur_p->app0 = STS_CTRL_APP0_IRQONEND;
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cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
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XTE_MAX_JUMBO_FRAME_SIZE,
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@ -663,7 +728,7 @@ static void ll_temac_recv(struct net_device *ndev)
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cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
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bdstat = cur_p->app0;
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}
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temac_dma_out32(lp, RX_TAILDESC_PTR, tail_p);
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lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
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spin_unlock_irqrestore(&lp->rx_lock, flags);
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}
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@ -674,8 +739,8 @@ static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
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struct temac_local *lp = netdev_priv(ndev);
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unsigned int status;
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status = temac_dma_in32(lp, TX_IRQ_REG);
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temac_dma_out32(lp, TX_IRQ_REG, status);
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status = lp->dma_in(lp, TX_IRQ_REG);
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lp->dma_out(lp, TX_IRQ_REG, status);
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if (status & (IRQ_COAL | IRQ_DLY))
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temac_start_xmit_done(lp->ndev);
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@ -692,8 +757,8 @@ static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
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unsigned int status;
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/* Read and clear the status registers */
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status = temac_dma_in32(lp, RX_IRQ_REG);
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temac_dma_out32(lp, RX_IRQ_REG, status);
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status = lp->dma_in(lp, RX_IRQ_REG);
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lp->dma_out(lp, RX_IRQ_REG, status);
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if (status & (IRQ_COAL | IRQ_DLY))
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ll_temac_recv(lp->ndev);
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@ -794,7 +859,7 @@ static ssize_t temac_show_llink_regs(struct device *dev,
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int i, len = 0;
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for (i = 0; i < 0x11; i++)
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len += sprintf(buf + len, "%.8x%s", temac_dma_in32(lp, i),
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len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
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(i % 8) == 7 ? "\n" : " ");
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len += sprintf(buf + len, "\n");
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@ -820,7 +885,6 @@ temac_of_probe(struct of_device *op, const struct of_device_id *match)
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struct net_device *ndev;
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const void *addr;
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int size, rc = 0;
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unsigned int dcrs;
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/* Init network device structure */
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ndev = alloc_etherdev(sizeof(*lp));
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@ -870,13 +934,20 @@ temac_of_probe(struct of_device *op, const struct of_device_id *match)
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goto nodev;
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}
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dcrs = dcr_resource_start(np, 0);
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if (dcrs == 0) {
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dev_err(&op->dev, "could not get DMA register address\n");
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goto nodev;
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/* Setup the DMA register accesses, could be DCR or memory mapped */
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if (temac_dcr_setup(lp, op, np)) {
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/* no DCR in the device tree, try non-DCR */
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lp->sdma_regs = of_iomap(np, 0);
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if (lp->sdma_regs) {
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lp->dma_in = temac_dma_in32;
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lp->dma_out = temac_dma_out32;
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dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
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} else {
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dev_err(&op->dev, "unable to map DMA registers\n");
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goto nodev;
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}
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}
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lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
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dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
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lp->rx_irq = irq_of_parse_and_map(np, 0);
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lp->tx_irq = irq_of_parse_and_map(np, 1);
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