thermal/drivers/rockchip: Support RK3588 SoC in the thermal driver
The RK3588 SoC has seven temperature sensor ADC channels: - Chip Center - CPU Cluster 1 (Dual A76 "Big" Cores) - CPU Cluster 2 (Dual A76 "Big" Cores) - CPU Cluster 0 (Quad A55 "Little" Cores) - Power Domain Center - Graphics Processing Unit - Neural Processing Unit Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> [rebase, squash fixes] Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20230308112253.15659-7-sebastian.reichel@collabora.com
This commit is contained in:
Finley Xiao
Daniel Lezcano
Родитель
267f596585
Коммит
45d7b3867a
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@ -165,29 +165,49 @@ struct rockchip_thermal_data {
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#define TSADCV2_AUTO_CON 0x04
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#define TSADCV2_INT_EN 0x08
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#define TSADCV2_INT_PD 0x0c
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#define TSADCV3_AUTO_SRC_CON 0x0c
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#define TSADCV3_HT_INT_EN 0x14
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#define TSADCV3_HSHUT_GPIO_INT_EN 0x18
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#define TSADCV3_HSHUT_CRU_INT_EN 0x1c
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#define TSADCV3_INT_PD 0x24
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#define TSADCV3_HSHUT_PD 0x28
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#define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
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#define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
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#define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
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#define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
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#define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
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#define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
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#define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
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#define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
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#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
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#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
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#define TSADCV2_AUTO_PERIOD 0x68
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#define TSADCV2_AUTO_PERIOD_HT 0x6c
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#define TSADCV3_AUTO_PERIOD 0x154
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#define TSADCV3_AUTO_PERIOD_HT 0x158
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#define TSADCV2_AUTO_EN BIT(0)
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#define TSADCV2_AUTO_EN_MASK BIT(16)
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#define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
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#define TSADCV3_AUTO_SRC_EN(chn) BIT(chn)
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#define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn)
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#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
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#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
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#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
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#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
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#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
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#define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
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#define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
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#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
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#define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
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#define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
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#define TSADCV2_DATA_MASK 0xfff
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#define TSADCV3_DATA_MASK 0x3ff
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#define TSADCV4_DATA_MASK 0x1ff
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#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
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#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
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@ -198,6 +218,8 @@ struct rockchip_thermal_data {
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#define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
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#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
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#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
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#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
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#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
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#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
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@ -214,6 +236,12 @@ struct rockchip_thermal_data {
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#define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
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#define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
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#define RK3588_GRF0_TSADC_CON 0x0100
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#define RK3588_GRF0_TSADC_TRM (0xff0077 << 0)
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#define RK3588_GRF0_TSADC_SHUT_2CRU (0x30003 << 10)
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#define RK3588_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12)
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#define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
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#define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
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#define GRF_TSADC_VCM_EN_L (0x10001 << 7)
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@ -508,6 +536,15 @@ static const struct tsadc_table rk3568_code_table[] = {
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{TSADCV2_DATA_MASK, 125000},
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};
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static const struct tsadc_table rk3588_code_table[] = {
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{0, -40000},
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{215, -40000},
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{285, 25000},
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{350, 85000},
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{395, 125000},
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{TSADCV4_DATA_MASK, 125000},
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};
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static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
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int temp)
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{
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@ -778,6 +815,25 @@ static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs,
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}
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}
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static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs,
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enum tshut_polarity tshut_polarity)
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{
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writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
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writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME,
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regs + TSADCV3_AUTO_PERIOD_HT);
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writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
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regs + TSADCV3_HIGHT_INT_DEBOUNCE);
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writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
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regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
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if (tshut_polarity == TSHUT_HIGH_ACTIVE)
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writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
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TSADCV2_AUTO_TSHUT_POLARITY_MASK,
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regs + TSADCV2_AUTO_CON);
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else
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writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
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regs + TSADCV2_AUTO_CON);
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}
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static void rk_tsadcv2_irq_ack(void __iomem *regs)
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{
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u32 val;
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@ -794,6 +850,17 @@ static void rk_tsadcv3_irq_ack(void __iomem *regs)
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writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
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}
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static void rk_tsadcv4_irq_ack(void __iomem *regs)
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{
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u32 val;
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val = readl_relaxed(regs + TSADCV3_INT_PD);
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writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
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val = readl_relaxed(regs + TSADCV3_HSHUT_PD);
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writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
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regs + TSADCV3_HSHUT_PD);
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}
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static void rk_tsadcv2_control(void __iomem *regs, bool enable)
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{
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u32 val;
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@ -829,6 +896,18 @@ static void rk_tsadcv3_control(void __iomem *regs, bool enable)
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writel_relaxed(val, regs + TSADCV2_AUTO_CON);
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}
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static void rk_tsadcv4_control(void __iomem *regs, bool enable)
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{
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u32 val;
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if (enable)
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val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
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else
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val = TSADCV2_AUTO_EN_MASK;
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writel_relaxed(val, regs + TSADCV2_AUTO_CON);
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}
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static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
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int chn, void __iomem *regs, int *temp)
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{
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@ -839,6 +918,16 @@ static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
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return rk_tsadcv2_code_to_temp(table, val, temp);
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}
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static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
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int chn, void __iomem *regs, int *temp)
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{
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u32 val;
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val = readl_relaxed(regs + TSADCV3_DATA(chn));
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return rk_tsadcv2_code_to_temp(table, val, temp);
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}
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static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
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int chn, void __iomem *regs, int temp)
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{
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@ -873,6 +962,33 @@ static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
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return 0;
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}
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static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table,
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int chn, void __iomem *regs, int temp)
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{
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u32 alarm_value;
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/*
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* In some cases, some sensors didn't need the trip points, the
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* set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
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* in the end, ignore this case and disable the high temperature
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* interrupt.
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*/
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if (temp == INT_MAX) {
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writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
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regs + TSADCV3_HT_INT_EN);
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return 0;
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}
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/* Make sure the value is valid */
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alarm_value = rk_tsadcv2_temp_to_code(table, temp);
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if (alarm_value == table->data_mask)
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return -ERANGE;
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writel_relaxed(alarm_value & table->data_mask,
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regs + TSADCV3_COMP_INT(chn));
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writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
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regs + TSADCV3_HT_INT_EN);
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return 0;
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}
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static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
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int chn, void __iomem *regs, int temp)
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{
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@ -892,6 +1008,25 @@ static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
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return 0;
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}
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static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table,
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int chn, void __iomem *regs, int temp)
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{
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u32 tshut_value;
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/* Make sure the value is valid */
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tshut_value = rk_tsadcv2_temp_to_code(table, temp);
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if (tshut_value == table->data_mask)
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return -ERANGE;
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writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
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/* TSHUT will be valid */
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writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
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regs + TSADCV3_AUTO_SRC_CON);
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return 0;
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}
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static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
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enum tshut_mode mode)
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{
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@ -909,6 +1044,22 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
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writel_relaxed(val, regs + TSADCV2_INT_EN);
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}
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static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs,
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enum tshut_mode mode)
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{
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u32 val_gpio, val_cru;
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if (mode == TSHUT_MODE_GPIO) {
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val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
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val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
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} else {
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val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
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val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
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}
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writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
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writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
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}
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static const struct rockchip_tsadc_chip px30_tsadc_data = {
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/* cpu, gpu */
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.chn_offset = 0,
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@ -1132,6 +1283,28 @@ static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
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},
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};
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static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
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/* top, big_core0, big_core1, little_core, center, gpu, npu */
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.chn_offset = 0,
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.chn_num = 7, /* seven channels for tsadc */
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.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
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.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
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.tshut_temp = 95000,
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.initialize = rk_tsadcv8_initialize,
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.irq_ack = rk_tsadcv4_irq_ack,
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.control = rk_tsadcv4_control,
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.get_temp = rk_tsadcv4_get_temp,
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.set_alarm_temp = rk_tsadcv3_alarm_temp,
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.set_tshut_temp = rk_tsadcv3_tshut_temp,
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.set_tshut_mode = rk_tsadcv3_tshut_mode,
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.table = {
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.id = rk3588_code_table,
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.length = ARRAY_SIZE(rk3588_code_table),
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.data_mask = TSADCV4_DATA_MASK,
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.mode = ADC_INCREMENT,
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},
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};
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static const struct of_device_id of_rockchip_thermal_match[] = {
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{ .compatible = "rockchip,px30-tsadc",
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.data = (void *)&px30_tsadc_data,
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@ -1168,6 +1341,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = {
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.compatible = "rockchip,rk3568-tsadc",
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.data = (void *)&rk3568_tsadc_data,
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},
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{
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.compatible = "rockchip,rk3588-tsadc",
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.data = (void *)&rk3588_tsadc_data,
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},
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{ /* end */ },
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};
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MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
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