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PCI: change PCI nomenclature in drivers/pci/ (comment changes) 

Changing occurrences of variants of PCI-X and PCIe to the PCI-SIG
terms listed in the "Trademark and Logo Usage Guidelines".
http://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf

Patch is limited to drivers/pci/ and changes concern comments only.

Signed-off-by: Stefan Assmann <sassmann@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Stefan Assmann 2009-12-03 06:49:24 -05:00 коммит произвёл Jesse Barnes
Родитель 5714868812
Коммит 45e829ea41
10 изменённых файлов: 20 добавлений и 20 удалений
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2
drivers/pci/hotplug/shpchp.h
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@ -121,7 +121,7 @@ struct controller {
#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450 #define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458 #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
/* AMD PCIX bridge registers */ /* AMD PCI-X bridge registers */
#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
#define PCIX_MISCII_OFFSET 0x48 #define PCIX_MISCII_OFFSET 0x48
#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80

6
drivers/pci/intel-iommu.c
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@ -304,7 +304,7 @@ struct device_domain_info {
int segment; /* PCI domain */ int segment; /* PCI domain */
u8 bus; /* PCI bus number */ u8 bus; /* PCI bus number */
u8 devfn; /* PCI devfn number */ u8 devfn; /* PCI devfn number */
struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */ struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
struct intel_iommu *iommu; /* IOMMU used by this device */ struct intel_iommu *iommu; /* IOMMU used by this device */
struct dmar_domain *domain; /* pointer to domain */ struct dmar_domain *domain; /* pointer to domain */
}; };
@ -1611,7 +1611,7 @@ domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
return ret; return ret;
parent = parent->bus->self; parent = parent->bus->self;
} }
if (pci_is_pcie(tmp)) /* this is a PCIE-to-PCI bridge */ if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
return domain_context_mapping_one(domain, return domain_context_mapping_one(domain,
pci_domain_nr(tmp->subordinate), pci_domain_nr(tmp->subordinate),
tmp->subordinate->number, 0, tmp->subordinate->number, 0,
@ -3319,7 +3319,7 @@ static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
parent->devfn); parent->devfn);
parent = parent->bus->self; parent = parent->bus->self;
} }
if (pci_is_pcie(tmp)) /* this is a PCIE-to-PCI bridge */ if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
iommu_detach_dev(iommu, iommu_detach_dev(iommu,
tmp->subordinate->number, 0); tmp->subordinate->number, 0);
else /* this is a legacy PCI bridge */ else /* this is a legacy PCI bridge */

2
drivers/pci/intr_remapping.c
Просмотреть файл

@ -528,7 +528,7 @@ int set_msi_sid(struct irte *irte, struct pci_dev *dev)
bridge = pci_find_upstream_pcie_bridge(dev); bridge = pci_find_upstream_pcie_bridge(dev);
if (bridge) { if (bridge) {
if (pci_is_pcie(bridge))/* this is a PCIE-to-PCI/PCIX bridge */ if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */
set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
(bridge->bus->number << 8) | dev->bus->number); (bridge->bus->number << 8) | dev->bus->number);
else /* this is a legacy PCI bridge */ else /* this is a legacy PCI bridge */

6
drivers/pci/pci.c
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@ -1153,11 +1153,11 @@ pci_disable_device(struct pci_dev *dev)
/** /**
* pcibios_set_pcie_reset_state - set reset state for device dev * pcibios_set_pcie_reset_state - set reset state for device dev
* @dev: the PCI-E device reset * @dev: the PCIe device reset
* @state: Reset state to enter into * @state: Reset state to enter into
* *
* *
* Sets the PCI-E reset state for the device. This is the default * Sets the PCIe reset state for the device. This is the default
* implementation. Architecture implementations can override this. * implementation. Architecture implementations can override this.
*/ */
int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
@ -1168,7 +1168,7 @@ int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
/** /**
* pci_set_pcie_reset_state - set reset state for device dev * pci_set_pcie_reset_state - set reset state for device dev
* @dev: the PCI-E device reset * @dev: the PCIe device reset
* @state: Reset state to enter into * @state: Reset state to enter into
* *
* *

4
drivers/pci/pcie/aer/aer_inject.c
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@ -1,7 +1,7 @@
/* /*
* PCIE AER software error injection support. * PCIe AER software error injection support.
* *
* Debuging PCIE AER code is quite difficult because it is hard to * Debuging PCIe AER code is quite difficult because it is hard to
* trigger various real hardware errors. Software based error * trigger various real hardware errors. Software based error
* injection can fake almost all kinds of errors with the help of a * injection can fake almost all kinds of errors with the help of a
* user space helper tool aer-inject, which can be gotten from: * user space helper tool aer-inject, which can be gotten from:

2
drivers/pci/pcie/aer/aerdrv.c
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@ -155,7 +155,7 @@ static struct aer_rpc *aer_alloc_rpc(struct pcie_device *dev)
mutex_init(&rpc->rpc_mutex); mutex_init(&rpc->rpc_mutex);
init_waitqueue_head(&rpc->wait_release); init_waitqueue_head(&rpc->wait_release);
/* Use PCIE bus function to store rpc into PCIE device */ /* Use PCIe bus function to store rpc into PCIe device */
set_service_data(dev, rpc); set_service_data(dev, rpc);
return rpc; return rpc;

2
drivers/pci/pcie/aer/aerdrv_acpi.c
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@ -24,7 +24,7 @@
* *
* @return: Zero on success. Nonzero otherwise. * @return: Zero on success. Nonzero otherwise.
* *
* Invoked when PCIE bus loads AER service driver. To avoid conflict with * Invoked when PCIe bus loads AER service driver. To avoid conflict with
* BIOS AER support requires BIOS to yield AER control to OS native driver. * BIOS AER support requires BIOS to yield AER control to OS native driver.
**/ **/
int aer_osc_setup(struct pcie_device *pciedev) int aer_osc_setup(struct pcie_device *pciedev)

6
drivers/pci/pcie/aer/aerdrv_core.c
Просмотреть файл

@ -587,7 +587,7 @@ static void handle_error_source(struct pcie_device *aerdev,
* aer_enable_rootport - enable Root Port's interrupts when receiving messages * aer_enable_rootport - enable Root Port's interrupts when receiving messages
* @rpc: pointer to a Root Port data structure * @rpc: pointer to a Root Port data structure
* *
* Invoked when PCIE bus loads AER service driver. * Invoked when PCIe bus loads AER service driver.
*/ */
void aer_enable_rootport(struct aer_rpc *rpc) void aer_enable_rootport(struct aer_rpc *rpc)
{ {
@ -597,7 +597,7 @@ void aer_enable_rootport(struct aer_rpc *rpc)
u32 reg32; u32 reg32;
pos = pci_pcie_cap(pdev); pos = pci_pcie_cap(pdev);
/* Clear PCIE Capability's Device Status */ /* Clear PCIe Capability's Device Status */
pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, &reg16); pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, &reg16);
pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16); pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16);
@ -631,7 +631,7 @@ void aer_enable_rootport(struct aer_rpc *rpc)
* disable_root_aer - disable Root Port's interrupts when receiving messages * disable_root_aer - disable Root Port's interrupts when receiving messages
* @rpc: pointer to a Root Port data structure * @rpc: pointer to a Root Port data structure
* *
* Invoked when PCIE bus unloads AER service driver. * Invoked when PCIe bus unloads AER service driver.
*/ */
static void disable_root_aer(struct aer_rpc *rpc) static void disable_root_aer(struct aer_rpc *rpc)
{ {

4
drivers/pci/pcie/aspm.c
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@ -1,6 +1,6 @@
/* /*
* File: drivers/pci/pcie/aspm.c * File: drivers/pci/pcie/aspm.c
* Enabling PCIE link L0s/L1 state and Clock Power Management * Enabling PCIe link L0s/L1 state and Clock Power Management
* *
* Copyright (C) 2007 Intel * Copyright (C) 2007 Intel
* Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
@ -499,7 +499,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
int pos; int pos;
u32 reg32; u32 reg32;
/* /*
* Some functions in a slot might not all be PCIE functions, * Some functions in a slot might not all be PCIe functions,
* very strange. Disable ASPM for the whole slot * very strange. Disable ASPM for the whole slot
*/ */
list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {

6
drivers/pci/search.c
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@ -15,9 +15,9 @@
DECLARE_RWSEM(pci_bus_sem); DECLARE_RWSEM(pci_bus_sem);
/* /*
* find the upstream PCIE-to-PCI bridge of a PCI device * find the upstream PCIe-to-PCI bridge of a PCI device
* if the device is PCIE, return NULL * if the device is PCIE, return NULL
* if the device isn't connected to a PCIE bridge (that is its parent is a * if the device isn't connected to a PCIe bridge (that is its parent is a
* legacy PCI bridge and the bridge is directly connected to bus 0), return its * legacy PCI bridge and the bridge is directly connected to bus 0), return its
* parent * parent
*/ */
@ -37,7 +37,7 @@ pci_find_upstream_pcie_bridge(struct pci_dev *pdev)
tmp = pdev; tmp = pdev;
continue; continue;
} }
/* PCI device should connect to a PCIE bridge */ /* PCI device should connect to a PCIe bridge */
if (pdev->pcie_type != PCI_EXP_TYPE_PCI_BRIDGE) { if (pdev->pcie_type != PCI_EXP_TYPE_PCI_BRIDGE) {
/* Busted hardware? */ /* Busted hardware? */
WARN_ON_ONCE(1); WARN_ON_ONCE(1);