[SPARC64]: Sanitize %pstate writes for sun4v.
If we're just switching between different alternate global sets, nop it out on sun4v. Also, get rid of all of the alternate global save/restore in the OBP CIF trampoline code. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Родитель
314981ac71
Коммит
45fec05f80
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@ -60,8 +60,15 @@ kvmap_itlb_load:
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retry
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kvmap_itlb_longpath:
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rdpr %pstate, %g5
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661: rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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.section .gl_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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rdpr %tpc, %g5
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ba,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_ITLB, %g4
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@ -161,8 +168,15 @@ kvmap_check_obp:
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nop
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kvmap_dtlb_longpath:
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rdpr %pstate, %g5
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661: rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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.section .gl_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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rdpr %tl, %g4
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cmp %g4, 1
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mov TLB_TAG_ACCESS, %g4
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@ -547,19 +547,33 @@ static void __init per_cpu_patch(void)
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static void __init gl_patch(void)
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{
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struct gl_1insn_patch_entry *p;
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struct gl_1insn_patch_entry *p1;
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struct gl_2insn_patch_entry *p2;
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if (tlb_type != hypervisor)
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return;
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p = &__gl_1insn_patch;
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while (p < &__gl_1insn_patch_end) {
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unsigned long addr = p->addr;
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p1 = &__gl_1insn_patch;
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while (p1 < &__gl_1insn_patch_end) {
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unsigned long addr = p1->addr;
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*(unsigned int *) (addr + 0) = p->insn;
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*(unsigned int *) (addr + 0) = p1->insn;
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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p++;
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p1++;
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}
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p2 = &__gl_2insn_patch;
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while (p2 < &__gl_2insn_patch_end) {
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unsigned long addr = p2->addr;
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*(unsigned int *) (addr + 0) = p2->insns[0];
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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*(unsigned int *) (addr + 3) = p2->insns[1];
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__asm__ __volatile__("flush %0" : : "r" (addr + 4));
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p2++;
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}
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}
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@ -82,9 +82,17 @@ tsb_itlb_load:
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.globl tsb_do_fault
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tsb_do_fault:
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cmp %g3, FAULT_CODE_DTLB
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rdpr %pstate, %g5
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bne,pn %xcc, tsb_do_itlb_fault
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661: rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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.section .gl_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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bne,pn %xcc, tsb_do_itlb_fault
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nop
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tsb_do_dtlb_fault:
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rdpr %tl, %g4
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@ -80,6 +80,9 @@ SECTIONS
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__gl_1insn_patch = .;
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.gl_1insn_patch : { *(.gl_1insn_patch) }
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__gl_1insn_patch_end = .;
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__gl_2insn_patch = .;
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.gl_2insn_patch : { *(.gl_2insn_patch) }
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__gl_2insn_patch_end = .;
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. = ALIGN(8192);
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__initramfs_start = .;
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.init.ramfs : { *(.init.ramfs) }
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@ -444,8 +444,15 @@ xcall_flush_tlb_kernel_range: /* 22 insns */
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*/
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.globl xcall_sync_tick
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xcall_sync_tick:
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rdpr %pstate, %g2
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661: rdpr %pstate, %g2
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wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
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.section .gl_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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rdpr %pil, %g2
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wrpr %g0, 15, %pil
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sethi %hi(109f), %g7
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@ -468,8 +475,15 @@ xcall_sync_tick:
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*/
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.globl xcall_report_regs
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xcall_report_regs:
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rdpr %pstate, %g2
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661: rdpr %pstate, %g2
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wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
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.section .gl_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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rdpr %pil, %g2
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wrpr %g0, 15, %pil
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sethi %hi(109f), %g7
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@ -1,10 +1,12 @@
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/* cif.S: PROM entry/exit assembler trampolines.
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*
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* Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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* Copyright (C) 2005 David S. Miller <davem@davemloft.net>
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* Copyright (C) 1996, 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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* Copyright (C) 2005, 2006 David S. Miller <davem@davemloft.net>
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*/
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#include <asm/pstate.h>
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#include <asm/cpudata.h>
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#include <asm/thread_info.h>
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.text
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.globl prom_cif_interface
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@ -12,78 +14,16 @@ prom_cif_interface:
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sethi %hi(p1275buf), %o0
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or %o0, %lo(p1275buf), %o0
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ldx [%o0 + 0x010], %o1 ! prom_cif_stack
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save %o1, -0x190, %sp
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save %o1, -192, %sp
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ldx [%i0 + 0x008], %l2 ! prom_cif_handler
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rdpr %pstate, %l4
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wrpr %g0, 0x15, %pstate ! save alternate globals
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stx %g1, [%sp + 2047 + 0x0b0]
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stx %g2, [%sp + 2047 + 0x0b8]
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stx %g3, [%sp + 2047 + 0x0c0]
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stx %g4, [%sp + 2047 + 0x0c8]
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stx %g5, [%sp + 2047 + 0x0d0]
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stx %g6, [%sp + 2047 + 0x0d8]
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stx %g7, [%sp + 2047 + 0x0e0]
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wrpr %g0, 0x814, %pstate ! save interrupt globals
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stx %g1, [%sp + 2047 + 0x0e8]
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stx %g2, [%sp + 2047 + 0x0f0]
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stx %g3, [%sp + 2047 + 0x0f8]
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stx %g4, [%sp + 2047 + 0x100]
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stx %g5, [%sp + 2047 + 0x108]
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stx %g6, [%sp + 2047 + 0x110]
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stx %g7, [%sp + 2047 + 0x118]
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wrpr %g0, 0x14, %pstate ! save normal globals
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stx %g1, [%sp + 2047 + 0x120]
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stx %g2, [%sp + 2047 + 0x128]
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stx %g3, [%sp + 2047 + 0x130]
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stx %g4, [%sp + 2047 + 0x138]
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stx %g5, [%sp + 2047 + 0x140]
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stx %g6, [%sp + 2047 + 0x148]
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stx %g7, [%sp + 2047 + 0x150]
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wrpr %g0, 0x414, %pstate ! save mmu globals
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stx %g1, [%sp + 2047 + 0x158]
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stx %g2, [%sp + 2047 + 0x160]
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stx %g3, [%sp + 2047 + 0x168]
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stx %g4, [%sp + 2047 + 0x170]
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stx %g5, [%sp + 2047 + 0x178]
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stx %g6, [%sp + 2047 + 0x180]
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stx %g7, [%sp + 2047 + 0x188]
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mov %g1, %l0 ! also save to locals, so we can handle
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mov %g2, %l1 ! tlb faults later on, when accessing
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mov %g3, %l3 ! the stack.
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mov %g7, %l5
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wrpr %l4, PSTATE_IE, %pstate ! turn off interrupts
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mov %g4, %l0
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mov %g5, %l1
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mov %g6, %l3
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call %l2
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add %i0, 0x018, %o0 ! prom_args
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wrpr %g0, 0x414, %pstate ! restore mmu globals
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mov %l0, %g1
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mov %l1, %g2
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mov %l3, %g3
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mov %l5, %g7
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wrpr %g0, 0x14, %pstate ! restore normal globals
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ldx [%sp + 2047 + 0x120], %g1
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ldx [%sp + 2047 + 0x128], %g2
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ldx [%sp + 2047 + 0x130], %g3
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ldx [%sp + 2047 + 0x138], %g4
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ldx [%sp + 2047 + 0x140], %g5
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ldx [%sp + 2047 + 0x148], %g6
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ldx [%sp + 2047 + 0x150], %g7
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wrpr %g0, 0x814, %pstate ! restore interrupt globals
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ldx [%sp + 2047 + 0x0e8], %g1
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ldx [%sp + 2047 + 0x0f0], %g2
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ldx [%sp + 2047 + 0x0f8], %g3
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ldx [%sp + 2047 + 0x100], %g4
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ldx [%sp + 2047 + 0x108], %g5
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ldx [%sp + 2047 + 0x110], %g6
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ldx [%sp + 2047 + 0x118], %g7
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wrpr %g0, 0x15, %pstate ! restore alternate globals
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ldx [%sp + 2047 + 0x0b0], %g1
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ldx [%sp + 2047 + 0x0b8], %g2
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ldx [%sp + 2047 + 0x0c0], %g3
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ldx [%sp + 2047 + 0x0c8], %g4
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ldx [%sp + 2047 + 0x0d0], %g5
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ldx [%sp + 2047 + 0x0d8], %g6
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ldx [%sp + 2047 + 0x0e0], %g7
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wrpr %l4, 0, %pstate ! restore original pstate
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mov %l0, %g4
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mov %l1, %g5
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mov %l3, %g6
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ret
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restore
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@ -91,135 +31,18 @@ prom_cif_interface:
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prom_cif_callback:
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sethi %hi(p1275buf), %o1
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or %o1, %lo(p1275buf), %o1
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save %sp, -0x270, %sp
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rdpr %pstate, %l4
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wrpr %g0, 0x15, %pstate ! save PROM alternate globals
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stx %g1, [%sp + 2047 + 0x0b0]
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stx %g2, [%sp + 2047 + 0x0b8]
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stx %g3, [%sp + 2047 + 0x0c0]
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stx %g4, [%sp + 2047 + 0x0c8]
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stx %g5, [%sp + 2047 + 0x0d0]
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stx %g6, [%sp + 2047 + 0x0d8]
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stx %g7, [%sp + 2047 + 0x0e0]
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! restore Linux alternate globals
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ldx [%sp + 2047 + 0x190], %g1
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ldx [%sp + 2047 + 0x198], %g2
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ldx [%sp + 2047 + 0x1a0], %g3
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ldx [%sp + 2047 + 0x1a8], %g4
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ldx [%sp + 2047 + 0x1b0], %g5
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ldx [%sp + 2047 + 0x1b8], %g6
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ldx [%sp + 2047 + 0x1c0], %g7
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wrpr %g0, 0x814, %pstate ! save PROM interrupt globals
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stx %g1, [%sp + 2047 + 0x0e8]
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stx %g2, [%sp + 2047 + 0x0f0]
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stx %g3, [%sp + 2047 + 0x0f8]
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stx %g4, [%sp + 2047 + 0x100]
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stx %g5, [%sp + 2047 + 0x108]
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stx %g6, [%sp + 2047 + 0x110]
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stx %g7, [%sp + 2047 + 0x118]
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! restore Linux interrupt globals
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ldx [%sp + 2047 + 0x1c8], %g1
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ldx [%sp + 2047 + 0x1d0], %g2
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ldx [%sp + 2047 + 0x1d8], %g3
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ldx [%sp + 2047 + 0x1e0], %g4
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ldx [%sp + 2047 + 0x1e8], %g5
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ldx [%sp + 2047 + 0x1f0], %g6
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ldx [%sp + 2047 + 0x1f8], %g7
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wrpr %g0, 0x14, %pstate ! save PROM normal globals
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stx %g1, [%sp + 2047 + 0x120]
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stx %g2, [%sp + 2047 + 0x128]
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stx %g3, [%sp + 2047 + 0x130]
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stx %g4, [%sp + 2047 + 0x138]
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stx %g5, [%sp + 2047 + 0x140]
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stx %g6, [%sp + 2047 + 0x148]
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stx %g7, [%sp + 2047 + 0x150]
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! restore Linux normal globals
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ldx [%sp + 2047 + 0x200], %g1
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ldx [%sp + 2047 + 0x208], %g2
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ldx [%sp + 2047 + 0x210], %g3
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ldx [%sp + 2047 + 0x218], %g4
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ldx [%sp + 2047 + 0x220], %g5
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ldx [%sp + 2047 + 0x228], %g6
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ldx [%sp + 2047 + 0x230], %g7
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wrpr %g0, 0x414, %pstate ! save PROM mmu globals
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stx %g1, [%sp + 2047 + 0x158]
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stx %g2, [%sp + 2047 + 0x160]
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stx %g3, [%sp + 2047 + 0x168]
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stx %g4, [%sp + 2047 + 0x170]
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stx %g5, [%sp + 2047 + 0x178]
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stx %g6, [%sp + 2047 + 0x180]
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stx %g7, [%sp + 2047 + 0x188]
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! restore Linux mmu globals
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ldx [%sp + 2047 + 0x238], %o0
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ldx [%sp + 2047 + 0x240], %o1
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ldx [%sp + 2047 + 0x248], %l2
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ldx [%sp + 2047 + 0x250], %l3
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ldx [%sp + 2047 + 0x258], %l5
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ldx [%sp + 2047 + 0x260], %l6
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ldx [%sp + 2047 + 0x268], %l7
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! switch to Linux tba
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sethi %hi(sparc64_ttable_tl0), %l1
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rdpr %tba, %l0 ! save PROM tba
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mov %o0, %g1
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mov %o1, %g2
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mov %l2, %g3
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mov %l3, %g4
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mov %l5, %g5
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mov %l6, %g6
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mov %l7, %g7
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wrpr %l1, %tba ! install Linux tba
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wrpr %l4, 0, %pstate ! restore PSTATE
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save %sp, -192, %sp
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TRAP_LOAD_THREAD_REG(%g6, %g1)
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LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %o0)
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ldx [%g6 + TI_TASK], %g4
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call prom_world
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mov %g0, %o0
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mov 0, %o0
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ldx [%i1 + 0x000], %l2
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call %l2
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mov %i0, %o0
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mov %o0, %l1
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call prom_world
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or %g0, 1, %o0
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wrpr %g0, 0x14, %pstate ! interrupts off
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! restore PROM mmu globals
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ldx [%sp + 2047 + 0x158], %o0
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ldx [%sp + 2047 + 0x160], %o1
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ldx [%sp + 2047 + 0x168], %l2
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ldx [%sp + 2047 + 0x170], %l3
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ldx [%sp + 2047 + 0x178], %l5
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ldx [%sp + 2047 + 0x180], %l6
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ldx [%sp + 2047 + 0x188], %l7
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wrpr %g0, 0x414, %pstate ! restore PROM mmu globals
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mov %o0, %g1
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mov %o1, %g2
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mov %l2, %g3
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mov %l3, %g4
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mov %l5, %g5
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mov %l6, %g6
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mov %l7, %g7
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wrpr %l0, %tba ! restore PROM tba
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wrpr %g0, 0x14, %pstate ! restore PROM normal globals
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ldx [%sp + 2047 + 0x120], %g1
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ldx [%sp + 2047 + 0x128], %g2
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ldx [%sp + 2047 + 0x130], %g3
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ldx [%sp + 2047 + 0x138], %g4
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ldx [%sp + 2047 + 0x140], %g5
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ldx [%sp + 2047 + 0x148], %g6
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ldx [%sp + 2047 + 0x150], %g7
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wrpr %g0, 0x814, %pstate ! restore PROM interrupt globals
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ldx [%sp + 2047 + 0x0e8], %g1
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ldx [%sp + 2047 + 0x0f0], %g2
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ldx [%sp + 2047 + 0x0f8], %g3
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ldx [%sp + 2047 + 0x100], %g4
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ldx [%sp + 2047 + 0x108], %g5
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ldx [%sp + 2047 + 0x110], %g6
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ldx [%sp + 2047 + 0x118], %g7
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wrpr %g0, 0x15, %pstate ! restore PROM alternate globals
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ldx [%sp + 2047 + 0x0b0], %g1
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ldx [%sp + 2047 + 0x0b8], %g2
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ldx [%sp + 2047 + 0x0c0], %g3
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ldx [%sp + 2047 + 0x0c8], %g4
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ldx [%sp + 2047 + 0x0d0], %g5
|
||||
ldx [%sp + 2047 + 0x0d8], %g6
|
||||
ldx [%sp + 2047 + 0x0e0], %g7
|
||||
wrpr %l4, 0, %pstate
|
||||
mov 1, %o0
|
||||
ret
|
||||
restore %l1, 0, %o0
|
||||
|
||||
|
|
|
|||
|
|
@ -78,6 +78,12 @@ struct gl_1insn_patch_entry {
|
|||
unsigned int insn;
|
||||
};
|
||||
extern struct gl_1insn_patch_entry __gl_1insn_patch, __gl_1insn_patch_end;
|
||||
|
||||
struct gl_2insn_patch_entry {
|
||||
unsigned int addr;
|
||||
unsigned int insns[2];
|
||||
};
|
||||
extern struct gl_2insn_patch_entry __gl_2insn_patch, __gl_2insn_patch_end;
|
||||
#endif /* !(__ASSEMBLY__) */
|
||||
|
||||
#define TRAP_PER_CPU_THREAD 0x00
|
||||
|
|
|
|||
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