mtd: spi-nor: micron-st: Rework spi_nor_micron_octal_dtr_enable()
Introduce template operation to remove code duplication. Split spi_nor_micron_octal_dtr_enable() in spi_nor_micron_octal_dtr_en() and spi_nor_micron_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to follow. Add dev_dbg messages in case spi_nor_read_id() fails. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-8-tudor.ambarus@microchip.com
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@ -28,75 +28,43 @@
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#define FSR_P_ERR BIT(4) /* Program operation status */
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#define FSR_PT_ERR BIT(1) /* Protection error bit */
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static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
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/* Micron ST SPI NOR flash operations. */
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#define MICRON_ST_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \
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SPI_MEM_OP_ADDR(naddr, addr, 0), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
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static int micron_st_nor_octal_dtr_en(struct spi_nor *nor)
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{
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struct spi_mem_op op;
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u8 *buf = nor->bouncebuf;
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int ret;
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if (enable) {
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/* Use 20 dummy cycles for memory array reads. */
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ret = spi_nor_write_enable(nor);
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if (ret)
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return ret;
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*buf = 20;
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op = (struct spi_mem_op)
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
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SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(1, buf, 1));
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ret = spi_mem_exec_op(nor->spimem, &op);
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if (ret)
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return ret;
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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return ret;
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}
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ret = spi_nor_write_enable(nor);
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/* Use 20 dummy cycles for memory array reads. */
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*buf = 20;
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op = (struct spi_mem_op)
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MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf);
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ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
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if (ret)
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return ret;
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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return ret;
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if (enable) {
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buf[0] = SPINOR_MT_OCT_DTR;
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} else {
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/*
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* The register is 1-byte wide, but 1-byte transactions are not
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* allowed in 8D-8D-8D mode. The next register is the dummy
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* cycle configuration register. Since the transaction needs to
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* be at least 2 bytes wide, set the next register to its
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* default value. This also makes sense because the value was
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* changed when enabling 8D-8D-8D mode, it should be reset when
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* disabling.
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*/
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buf[0] = SPINOR_MT_EXSPI;
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buf[1] = SPINOR_REG_MT_CFR1V_DEF;
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}
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buf[0] = SPINOR_MT_OCT_DTR;
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op = (struct spi_mem_op)
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
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SPI_MEM_OP_ADDR(enable ? 3 : 4,
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SPINOR_REG_MT_CFR0V, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
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if (!enable)
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spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
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ret = spi_mem_exec_op(nor->spimem, &op);
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MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR0V, 1, buf);
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ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
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if (ret)
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return ret;
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/* Read flash ID to make sure the switch was successful. */
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if (enable)
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ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR);
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else
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ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
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if (ret)
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ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR);
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if (ret) {
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dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
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return ret;
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}
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if (memcmp(buf, nor->info->id, nor->info->id_len))
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return -EINVAL;
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@ -104,6 +72,47 @@ static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
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return 0;
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}
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static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor)
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{
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struct spi_mem_op op;
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u8 *buf = nor->bouncebuf;
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int ret;
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/*
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* The register is 1-byte wide, but 1-byte transactions are not allowed
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* in 8D-8D-8D mode. The next register is the dummy cycle configuration
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* register. Since the transaction needs to be at least 2 bytes wide,
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* set the next register to its default value. This also makes sense
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* because the value was changed when enabling 8D-8D-8D mode, it should
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* be reset when disabling.
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*/
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buf[0] = SPINOR_MT_EXSPI;
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buf[1] = SPINOR_REG_MT_CFR1V_DEF;
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op = (struct spi_mem_op)
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MICRON_ST_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf);
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ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
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if (ret)
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return ret;
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/* Read flash ID to make sure the switch was successful. */
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ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
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if (ret) {
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dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
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return ret;
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}
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if (memcmp(buf, nor->info->id, nor->info->id_len))
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return -EINVAL;
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return 0;
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}
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static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
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{
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return enable ? micron_st_nor_octal_dtr_en(nor) :
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micron_st_nor_octal_dtr_dis(nor);
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}
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static void mt35xu512aba_default_init(struct spi_nor *nor)
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{
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nor->params->octal_dtr_enable = micron_st_nor_octal_dtr_enable;
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