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Few more omap fixes that are not regressions or oopses and can 

wait for the merge window.
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Merge tag 'omap-for-v3.13/fixes-not-urgent-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes-non-critical

From Tony Lindgren:
Few more omap fixes that are not regressions or oopses and can
wait for the merge window.

* tag 'omap-for-v3.13/fixes-not-urgent-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: irq, AM33XX add missing register check
  ARM: OMAP2+: wakeupgen: AM43x adaptation

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2013-10-28 13:58:12 -07:00
Родитель ffd076eea3 0bebda6848
Коммит 462fb38f3d
2 изменённых файлов: 14 добавлений и 6 удалений
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2
arch/arm/mach-omap2/irq.c
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@ -233,7 +233,7 @@ static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs
goto out;
irqnr = readl_relaxed(base_addr + 0xd8);
#ifdef CONFIG_SOC_TI81XX
#if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX)
if (irqnr)
goto out;
irqnr = readl_relaxed(base_addr + 0xf8);

18
arch/arm/mach-omap2/omap-wakeupgen.c
Просмотреть файл

@ -33,8 +33,12 @@
#include "omap4-sar-layout.h"
#include "common.h"
#define MAX_NR_REG_BANKS 5
#define MAX_IRQS 160
#define AM43XX_NR_REG_BANKS 7
#define AM43XX_IRQS 224
#define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS
#define MAX_IRQS AM43XX_IRQS
#define DEFAULT_NR_REG_BANKS 5
#define DEFAULT_IRQS 160
#define WKG_MASK_ALL 0x00000000
#define WKG_UNMASK_ALL 0xffffffff
#define CPU_ENA_OFFSET 0x400
@ -47,8 +51,8 @@ static void __iomem *wakeupgen_base;
static void __iomem *sar_base;
static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
static unsigned int irq_target_cpu[MAX_IRQS];
static unsigned int irq_banks = MAX_NR_REG_BANKS;
static unsigned int max_irqs = MAX_IRQS;
static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
static unsigned int max_irqs = DEFAULT_IRQS;
static unsigned int omap_secure_apis;
/*
@ -418,12 +422,16 @@ int __init omap_wakeupgen_init(void)
irq_banks = OMAP4_NR_BANKS;
max_irqs = OMAP4_NR_IRQS;
omap_secure_apis = 1;
} else if (soc_is_am43xx()) {
irq_banks = AM43XX_NR_REG_BANKS;
max_irqs = AM43XX_IRQS;
}
/* Clear all IRQ bitmasks at wakeupGen level */
for (i = 0; i < irq_banks; i++) {
wakeupgen_writel(0, i, CPU0_ID);
wakeupgen_writel(0, i, CPU1_ID);
if (!soc_is_am43xx())
wakeupgen_writel(0, i, CPU1_ID);
}
/*