ARM: dts: imx31: add device tree description of basic controllers
The change adds a number of basic peripherals found on i.MX31 SoC: * GPIO controllers, * I2C master controllers, * SPI master controllers, * ATA controller, * SDHC controllers, * RTC, watchdog and PWM contollers, * SDMA, * IRAM, * NAND and WEIM controllers on EMI. The added controller devices were tested on Freescale i.MX31 powered LogicPD Lite SoM and baseboard. DMA functionality was tested on SDHC and SPI controllers so far, thus dmas properties are added to those device nodes only. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Vladimir Zapolskiy
Shawn Guo
Родитель
82210bfd94
Коммит
465b3d77b1
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@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
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// Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
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/ {
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@ -15,11 +16,20 @@
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memory { device_type = "memory"; };
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aliases {
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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spi0 = &spi1;
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spi1 = &spi2;
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spi2 = &spi3;
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};
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cpus {
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@ -47,6 +57,14 @@
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interrupt-parent = <&avic>;
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ranges;
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iram: iram@1fffc000 {
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compatible = "mmio-sram";
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reg = <0x1fffc000 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1fffc000 0x4000>;
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};
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aips@43f00000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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@ -54,6 +72,34 @@
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reg = <0x43f00000 0x100000>;
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ranges;
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i2c1: i2c@43f80000 {
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compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
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reg = <0x43f80000 0x4000>;
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interrupts = <10>;
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clocks = <&clks 33>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@43f84000 {
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compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
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reg = <0x43f84000 0x4000>;
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interrupts = <3>;
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clocks = <&clks 35>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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ata: ata@43f8c000 {
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compatible = "fsl,imx31-pata", "fsl,imx27-pata";
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reg = <0x43f8c000 0x4000>;
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interrupts = <15>;
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clocks = <&clks 26>;
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status = "disabled";
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};
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uart1: serial@43f90000 {
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compatible = "fsl,imx31-uart", "fsl,imx21-uart";
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reg = <0x43f90000 0x4000>;
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@ -72,6 +118,29 @@
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status = "disabled";
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};
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i2c2: i2c@43f98000 {
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compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
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reg = <0x43f98000 0x4000>;
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interrupts = <4>;
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clocks = <&clks 34>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@43fa4000 {
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compatible = "fsl,imx31-cspi";
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reg = <0x43fa4000 0x4000>;
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interrupts = <14>;
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clocks = <&clks 10>, <&clks 53>;
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clock-names = "ipg", "per";
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dmas = <&sdma 8 8 0>, <&sdma 9 8 0>;
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dma-names = "rx", "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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kpp: kpp@43fa8000 {
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compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
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reg = <0x43fa8000 0x4000>;
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@ -106,6 +175,28 @@
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reg = <0x50000000 0x100000>;
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ranges;
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sdhci1: sdhci@50004000 {
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compatible = "fsl,imx31-mmc";
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reg = <0x50004000 0x4000>;
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interrupts = <9>;
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clocks = <&clks 10>, <&clks 20>;
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clock-names = "ipg", "per";
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dmas = <&sdma 20 3 0>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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sdhci2: sdhci@50008000 {
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compatible = "fsl,imx31-mmc";
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reg = <0x50008000 0x4000>;
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interrupts = <8>;
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clocks = <&clks 10>, <&clks 21>;
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clock-names = "ipg", "per";
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dmas = <&sdma 21 3 0>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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uart3: serial@5000c000 {
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compatible = "fsl,imx31-uart", "fsl,imx21-uart";
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reg = <0x5000c000 0x4000>;
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@ -115,6 +206,19 @@
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status = "disabled";
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};
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spi2: cspi@50010000 {
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compatible = "fsl,imx31-cspi";
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reg = <0x50010000 0x4000>;
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interrupts = <13>;
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clocks = <&clks 10>, <&clks 54>;
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clock-names = "ipg", "per";
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dmas = <&sdma 6 8 0>, <&sdma 7 8 0>;
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dma-names = "rx", "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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iim: iim@5001c000 {
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compatible = "fsl,imx31-iim", "fsl,imx27-iim";
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reg = <0x5001c000 0x1000>;
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@ -137,6 +241,19 @@
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#clock-cells = <1>;
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};
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spi3: cspi@53f84000 {
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compatible = "fsl,imx31-cspi";
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reg = <0x53f84000 0x4000>;
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interrupts = <17>;
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clocks = <&clks 10>, <&clks 28>;
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clock-names = "ipg", "per";
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dmas = <&sdma 10 8 0>, <&sdma 11 8 0>;
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dma-names = "rx", "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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gpt: timer@53f90000 {
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compatible = "fsl,imx31-gpt";
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reg = <0x53f90000 0x4000>;
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@ -144,6 +261,112 @@
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clocks = <&clks 10>, <&clks 22>;
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clock-names = "ipg", "per";
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};
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gpio3: gpio@53fa4000 {
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compatible = "fsl,imx31-gpio";
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reg = <0x53fa4000 0x4000>;
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interrupts = <56>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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rng@53fb0000 {
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compatible = "fsl,imx31-rnga";
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reg = <0x53fb0000 0x4000>;
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interrupts = <22>;
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clocks = <&clks 29>;
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};
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gpio1: gpio@53fcc000 {
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compatible = "fsl,imx31-gpio";
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reg = <0x53fcc000 0x4000>;
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interrupts = <52>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@53fd0000 {
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compatible = "fsl,imx31-gpio";
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reg = <0x53fd0000 0x4000>;
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interrupts = <51>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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sdma: sdma@53fd4000 {
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compatible = "fsl,imx31-sdma";
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reg = <0x53fd4000 0x4000>;
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interrupts = <34>;
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clocks = <&clks 10>, <&clks 27>;
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clock-names = "ipg", "ahb";
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#dma-cells = <3>;
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fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
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};
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rtc: rtc@53fd8000 {
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compatible = "fsl,imx31-rtc", "fsl,imx21-rtc";
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reg = <0x53fd8000 0x4000>;
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interrupts = <25>;
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clocks = <&clks 2>, <&clks 40>;
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clock-names = "ref", "ipg";
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};
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wdog: wdog@53fdc000 {
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compatible = "fsl,imx31-wdt", "fsl,imx21-wdt";
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reg = <0x53fdc000 0x4000>;
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clocks = <&clks 41>;
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};
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pwm: pwm@53fe0000 {
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compatible = "fsl,imx31-pwm", "fsl,imx27-pwm";
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reg = <0x53fe0000 0x4000>;
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interrupts = <26>;
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clocks = <&clks 10>, <&clks 42>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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status = "disabled";
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};
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};
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emi@b8000000 { /* External Memory Interface */
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compatible = "simple-bus";
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reg = <0xb8000000 0x5000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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nfc: nand@b8000000 {
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compatible = "fsl,imx31-nand", "fsl,imx27-nand";
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reg = <0xb8000000 0x1000>;
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interrupts = <33>;
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clocks = <&clks 9>;
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dmas = <&sdma 30 17 0>;
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dma-names = "rx-tx";
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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weim: weim@b8002000 {
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compatible = "fsl,imx31-weim", "fsl,imx27-weim";
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reg = <0xb8002000 0x1000>;
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clocks = <&clks 56>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0xa0000000 0x08000000
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1 0 0xa8000000 0x08000000
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2 0 0xb0000000 0x02000000
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3 0 0xb2000000 0x02000000
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4 0 0xb4000000 0x02000000
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5 0 0xb6000000 0x02000000>;
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status = "disabled";
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};
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};
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};
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};
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