Merge tag 'amd-drm-fixes-6.2-2023-02-08' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.2-2023-02-08: amdgpu: - Flickering fixes for DCN 2.1, 3.1.2/3 - Re-enable S/G display on DCN 3.1.4 - Properly fix S/G display with AGP aperture enabled - Fix cursor offset with 180 rotation - SMU13 fixes - Use TGID for GPUVM traces - Fix oops on in fence error path - Don't run IB tests on hw rings when sw rings are in use Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230209045321.565132-1-alexander.deucher@amd.com
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Коммит
4684f5ce83
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@ -618,7 +618,13 @@ void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev)
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if (!ring || !ring->fence_drv.initialized)
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continue;
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if (!ring->no_scheduler)
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/*
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* Notice we check for sched.ops since there's some
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* override on the meaning of sched.ready by amdgpu.
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* The natural check would be sched.ready, which is
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* set as drm_sched_init() finishes...
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*/
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if (ring->sched.ops)
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drm_sched_fini(&ring->sched);
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for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
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@ -295,7 +295,7 @@ struct amdgpu_ring {
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#define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
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#define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib)))
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#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
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#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
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#define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)
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#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
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#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
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#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
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@ -974,7 +974,7 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
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trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
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min(nptes, 32u), dst, incr,
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upd_flags,
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vm->task_info.pid,
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vm->task_info.tgid,
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vm->immediate.fence_context);
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amdgpu_vm_pte_update_flags(params, to_amdgpu_bo_vm(pt),
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cursor.level, pe_start, dst,
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@ -6877,7 +6877,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
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.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
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.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
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.test_ring = gfx_v9_0_ring_test_ring,
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.test_ib = gfx_v9_0_ring_test_ib,
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.insert_nop = amdgpu_ring_insert_nop,
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.emit_switch_buffer = gfx_v9_ring_emit_sb,
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@ -641,7 +641,9 @@ static int soc21_common_early_init(void *handle)
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AMD_CG_SUPPORT_GFX_CGLS |
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AMD_CG_SUPPORT_REPEATER_FGCG |
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AMD_CG_SUPPORT_GFX_MGCG |
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AMD_CG_SUPPORT_HDP_SD;
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AMD_CG_SUPPORT_HDP_SD |
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AMD_CG_SUPPORT_ATHUB_MGCG |
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AMD_CG_SUPPORT_ATHUB_LS;
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adev->pg_flags = AMD_PG_SUPPORT_VCN |
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AMD_PG_SUPPORT_VCN_DPG |
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AMD_PG_SUPPORT_JPEG;
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@ -1184,24 +1184,38 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
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memset(pa_config, 0, sizeof(*pa_config));
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logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
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pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
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if (adev->apu_flags & AMD_APU_IS_RAVEN2)
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/*
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* Raven2 has a HW issue that it is unable to use the vram which
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* is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
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* workaround that increase system aperture high address (add 1)
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* to get rid of the VM fault and hardware hang.
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*/
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logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
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else
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logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
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agp_base = 0;
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agp_bot = adev->gmc.agp_start >> 24;
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agp_top = adev->gmc.agp_end >> 24;
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/* AGP aperture is disabled */
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if (agp_bot == agp_top) {
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logical_addr_low = adev->gmc.vram_start >> 18;
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if (adev->apu_flags & AMD_APU_IS_RAVEN2)
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/*
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* Raven2 has a HW issue that it is unable to use the vram which
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* is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
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* workaround that increase system aperture high address (add 1)
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* to get rid of the VM fault and hardware hang.
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*/
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logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
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else
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logical_addr_high = adev->gmc.vram_end >> 18;
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} else {
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logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
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if (adev->apu_flags & AMD_APU_IS_RAVEN2)
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/*
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* Raven2 has a HW issue that it is unable to use the vram which
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* is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
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* workaround that increase system aperture high address (add 1)
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* to get rid of the VM fault and hardware hang.
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*/
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logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
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else
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logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
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}
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pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
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page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
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page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
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@ -1499,10 +1513,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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(adev->apu_flags & AMD_APU_IS_PICASSO))
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init_data.flags.gpu_vm_support = true;
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break;
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case IP_VERSION(2, 1, 0):
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case IP_VERSION(3, 0, 1):
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case IP_VERSION(3, 1, 2):
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case IP_VERSION(3, 1, 3):
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case IP_VERSION(3, 1, 4):
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case IP_VERSION(3, 1, 6):
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init_data.flags.gpu_vm_support = true;
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break;
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@ -3626,7 +3626,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
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(int)hubp->curs_attr.width || pos_cpy.x
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<= (int)hubp->curs_attr.width +
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pipe_ctx->plane_state->src_rect.x) {
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pos_cpy.x = temp_x + viewport_width;
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pos_cpy.x = 2 * viewport_width - temp_x;
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}
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}
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} else {
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@ -1991,6 +1991,8 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
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case IP_VERSION(9, 4, 2):
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case IP_VERSION(10, 3, 0):
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case IP_VERSION(11, 0, 0):
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case IP_VERSION(11, 0, 1):
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case IP_VERSION(11, 0, 2):
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*states = ATTR_STATE_SUPPORTED;
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break;
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default:
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@ -123,7 +123,8 @@
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(1 << FEATURE_DS_FCLK_BIT) | \
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(1 << FEATURE_DS_LCLK_BIT) | \
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(1 << FEATURE_DS_DCFCLK_BIT) | \
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(1 << FEATURE_DS_UCLK_BIT))
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(1 << FEATURE_DS_UCLK_BIT) | \
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(1ULL << FEATURE_DS_VCN_BIT))
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//For use with feature control messages
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typedef enum {
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@ -522,9 +523,9 @@ typedef enum {
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TEMP_HOTSPOT_M,
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TEMP_MEM,
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TEMP_VR_GFX,
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TEMP_VR_SOC,
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TEMP_VR_MEM0,
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TEMP_VR_MEM1,
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TEMP_VR_SOC,
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TEMP_VR_U,
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TEMP_LIQUID0,
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TEMP_LIQUID1,
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@ -113,20 +113,21 @@
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#define NUM_FEATURES 64
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#define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL
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#define ALLOWED_FEATURE_CTRL_SCPM (1 << FEATURE_DPM_GFXCLK_BIT) | \
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(1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
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(1 << FEATURE_DPM_UCLK_BIT) | \
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(1 << FEATURE_DPM_FCLK_BIT) | \
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(1 << FEATURE_DPM_SOCCLK_BIT) | \
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(1 << FEATURE_DPM_MP0CLK_BIT) | \
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(1 << FEATURE_DPM_LINK_BIT) | \
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(1 << FEATURE_DPM_DCN_BIT) | \
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(1 << FEATURE_DS_GFXCLK_BIT) | \
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(1 << FEATURE_DS_SOCCLK_BIT) | \
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(1 << FEATURE_DS_FCLK_BIT) | \
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(1 << FEATURE_DS_LCLK_BIT) | \
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(1 << FEATURE_DS_DCFCLK_BIT) | \
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(1 << FEATURE_DS_UCLK_BIT)
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#define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \
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(1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
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(1 << FEATURE_DPM_UCLK_BIT) | \
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(1 << FEATURE_DPM_FCLK_BIT) | \
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(1 << FEATURE_DPM_SOCCLK_BIT) | \
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(1 << FEATURE_DPM_MP0CLK_BIT) | \
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(1 << FEATURE_DPM_LINK_BIT) | \
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(1 << FEATURE_DPM_DCN_BIT) | \
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(1 << FEATURE_DS_GFXCLK_BIT) | \
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(1 << FEATURE_DS_SOCCLK_BIT) | \
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(1 << FEATURE_DS_FCLK_BIT) | \
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(1 << FEATURE_DS_LCLK_BIT) | \
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(1 << FEATURE_DS_DCFCLK_BIT) | \
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(1 << FEATURE_DS_UCLK_BIT) | \
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(1ULL << FEATURE_DS_VCN_BIT))
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//For use with feature control messages
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typedef enum {
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@ -28,11 +28,11 @@
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#define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF
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#define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04
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#define SMU13_DRIVER_IF_VERSION_ALDE 0x08
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0 0x34
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0 0x37
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x07
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10 0x32
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x35
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x37
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_10 0x1D
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#define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
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@ -407,6 +407,9 @@ static int smu_v13_0_0_setup_pptable(struct smu_context *smu)
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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if (amdgpu_sriov_vf(smu->adev))
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return 0;
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ret = smu_v13_0_0_get_pptable_from_pmfw(smu,
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&smu_table->power_play_table,
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&smu_table->power_play_table_size);
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@ -1257,6 +1260,9 @@ static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
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table_context->power_play_table;
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PPTable_t *pptable = smu->smu_table.driver_pptable;
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if (amdgpu_sriov_vf(smu->adev))
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return 0;
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if (!range)
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return -EINVAL;
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@ -124,6 +124,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
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MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
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MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
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MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0),
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MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
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};
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static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
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