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staging: mt7621-pci: improve interrupt mapping 

As the Interrupts for the PCI adapters are listed in
devicetree we shouldn't need to have them explicit in the code.

The simplest way to do this is to use of_irq_parse_and_map_pci()
and specify an interrupt-map which identifies the different
PCI hosts by bus/slot numbers.
This has the advantage that the hwirq number are mapped to virq
numbers for us, so the ugly hack can go.

Signed-off-by: NeilBrown <neil@brown.name>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
NeilBrown 2018-05-04 14:58:36 +10:00 коммит произвёл Greg Kroah-Hartman
Родитель 66fbebb631
Коммит 46d093124d
2 изменённых файлов: 13 добавлений и 84 удалений
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9
drivers/staging/mt7621-dts/mt7621.dtsi
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@ -429,10 +429,11 @@
0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xF0000 0 0 1>;
interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
<0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
<0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";

88
drivers/staging/mt7621-pci/pci-mt7621.c
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@ -73,12 +73,6 @@ extern void chk_phy_pll(void);
#define RALINK_PCI_CONFIG_ADDR 0x20
#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
#define SURFBOARDINT_PCIE0 11 /* PCIE0 */
#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
#define SURFBOARDINT_PCIE1 31 /* PCIE1 */
#define SURFBOARDINT_PCIE2 32 /* PCIE2 */
#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
#define RALINK_PCIE0_RST (1<<24)
@ -367,68 +361,12 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
u16 cmd;
u32 val;
int irq = 0;
int irq;
if ((dev->bus->number == 0) && (slot == 0)) {
write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 0 = %x\n", val);
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
} else if((dev->bus->number == 0) && (slot == 0x1)) {
write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 1 = %x\n", val);
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
} else if((dev->bus->number == 0) && (slot == 0x2)) {
write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 2 = %x\n", val);
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
} else if ((dev->bus->number == 1) && (slot == 0x0)) {
switch (pcie_link_status) {
case 2:
case 6:
irq = RALINK_INT_PCIE1;
break;
case 4:
irq = RALINK_INT_PCIE2;
break;
default:
irq = RALINK_INT_PCIE0;
}
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number == 2) && (slot == 0x0)) {
switch (pcie_link_status) {
case 5:
case 6:
irq = RALINK_INT_PCIE2;
break;
default:
irq = RALINK_INT_PCIE1;
}
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number == 2) && (slot == 0x1)) {
switch (pcie_link_status) {
case 5:
case 6:
irq = RALINK_INT_PCIE2;
break;
default:
irq = RALINK_INT_PCIE1;
}
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x0)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x1)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x2)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else {
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
return 0;
if (dev->bus->number == 0) {
write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot %d = %x\n", slot, val);
}
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
@ -436,20 +374,10 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
pci_read_config_word(dev, PCI_COMMAND, &cmd);
cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
pci_write_config_word(dev, PCI_COMMAND, cmd);
irq = of_irq_parse_and_map_pci(dev, slot, pin);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
#ifdef CONFIG_DTB_GNUBEE1
/*
* 'irq' here is a hwirq, but a virq is needed. Until we know how and where
* to convert one to the other, we have this hack for the GNUBEE1
* Similarly 31->23 and 32->24.
*/
if (irq == 11)
return 22;
if (irq == 31)
return 23;
if (irq == 32)
return 24;
#endif
return irq;
}