Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
xdp_return_frame_bulk() needs to pass a xdp_buff to __xdp_return(). strlcpy got converted to strscpy but here it makes no functional difference, so just keep the right code. Conflicts: net/netfilter/nf_tables_api.c Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
Коммит
46d5e62dd3
2
.mailmap
2
.mailmap
|
|
@ -322,6 +322,8 @@ TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn>
|
|||
Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com>
|
||||
Tycho Andersen <tycho@tycho.pizza> <tycho@tycho.ws>
|
||||
Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
|
||||
Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
|
||||
Uwe Kleine-König <ukleinek@strlen.de>
|
||||
Uwe Kleine-König <ukl@pengutronix.de>
|
||||
Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
|
||||
Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
|
||||
|
|
|
|||
5
CREDITS
5
CREDITS
|
|
@ -740,6 +740,11 @@ S: (ask for current address)
|
|||
S: Portland, Oregon
|
||||
S: USA
|
||||
|
||||
N: Jason Cooper
|
||||
D: ARM/Marvell SOC co-maintainer
|
||||
D: irqchip co-maintainer
|
||||
D: MVEBU PCI DRIVER co-maintainer
|
||||
|
||||
N: Robin Cornelius
|
||||
E: robincornelius@users.sourceforge.net
|
||||
D: Ralink rt2x00 WLAN driver
|
||||
|
|
|
|||
28
MAINTAINERS
28
MAINTAINERS
|
|
@ -1486,10 +1486,20 @@ F: Documentation/devicetree/bindings/iommu/arm,smmu*
|
|||
F: drivers/iommu/arm/
|
||||
F: drivers/iommu/io-pgtable-arm*
|
||||
|
||||
ARM AND ARM64 SoC SUB-ARCHITECTURES (COMMON PARTS)
|
||||
M: Arnd Bergmann <arnd@arndb.de>
|
||||
M: Olof Johansson <olof@lixom.net>
|
||||
M: soc@kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
|
||||
F: arch/arm/boot/dts/Makefile
|
||||
F: arch/arm64/boot/dts/Makefile
|
||||
|
||||
ARM SUB-ARCHITECTURES
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
|
||||
F: arch/arm/mach-*/
|
||||
F: arch/arm/plat-*/
|
||||
|
||||
|
|
@ -2014,7 +2024,6 @@ M: Philipp Zabel <philipp.zabel@gmail.com>
|
|||
S: Maintained
|
||||
|
||||
ARM/Marvell Dove/MV78xx0/Orion SOC support
|
||||
M: Jason Cooper <jason@lakedaemon.net>
|
||||
M: Andrew Lunn <andrew@lunn.ch>
|
||||
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
||||
M: Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
|
@ -2031,7 +2040,6 @@ F: arch/arm/plat-orion/
|
|||
F: drivers/soc/dove/
|
||||
|
||||
ARM/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SOC support
|
||||
M: Jason Cooper <jason@lakedaemon.net>
|
||||
M: Andrew Lunn <andrew@lunn.ch>
|
||||
M: Gregory Clement <gregory.clement@bootlin.com>
|
||||
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
||||
|
|
@ -3239,7 +3247,7 @@ R: Martin KaFai Lau <kafai@fb.com>
|
|||
R: Song Liu <songliubraving@fb.com>
|
||||
R: Yonghong Song <yhs@fb.com>
|
||||
R: John Fastabend <john.fastabend@gmail.com>
|
||||
R: KP Singh <kpsingh@chromium.org>
|
||||
R: KP Singh <kpsingh@kernel.org>
|
||||
L: netdev@vger.kernel.org
|
||||
L: bpf@vger.kernel.org
|
||||
S: Supported
|
||||
|
|
@ -3358,7 +3366,7 @@ F: arch/x86/net/
|
|||
X: arch/x86/net/bpf_jit_comp32.c
|
||||
|
||||
BPF LSM (Security Audit and Enforcement using BPF)
|
||||
M: KP Singh <kpsingh@chromium.org>
|
||||
M: KP Singh <kpsingh@kernel.org>
|
||||
R: Florent Revest <revest@chromium.org>
|
||||
R: Brendan Jackman <jackmanb@chromium.org>
|
||||
L: bpf@vger.kernel.org
|
||||
|
|
@ -4287,6 +4295,7 @@ B: https://github.com/ClangBuiltLinux/linux/issues
|
|||
C: irc://chat.freenode.net/clangbuiltlinux
|
||||
F: Documentation/kbuild/llvm.rst
|
||||
F: scripts/clang-tools/
|
||||
F: scripts/lld-version.sh
|
||||
K: \b(?i:clang|llvm)\b
|
||||
|
||||
CLEANCACHE API
|
||||
|
|
@ -9249,7 +9258,6 @@ F: kernel/irq/
|
|||
|
||||
IRQCHIP DRIVERS
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Jason Cooper <jason@lakedaemon.net>
|
||||
M: Marc Zyngier <maz@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -10550,6 +10558,13 @@ S: Supported
|
|||
F: Documentation/networking/device_drivers/ethernet/marvell/octeontx2.rst
|
||||
F: drivers/net/ethernet/marvell/octeontx2/af/
|
||||
|
||||
MARVELL PRESTERA ETHERNET SWITCH DRIVER
|
||||
M: Vadym Kochan <vkochan@marvell.com>
|
||||
M: Taras Chornyi <tchornyi@marvell.com>
|
||||
S: Supported
|
||||
W: https://github.com/Marvell-switching/switchdev-prestera
|
||||
F: drivers/net/ethernet/marvell/prestera/
|
||||
|
||||
MARVELL SOC MMC/SD/SDIO CONTROLLER DRIVER
|
||||
M: Nicolas Pitre <nico@fluxnic.net>
|
||||
S: Odd Fixes
|
||||
|
|
@ -13398,7 +13413,6 @@ F: drivers/pci/controller/mobiveil/pcie-mobiveil*
|
|||
|
||||
PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
|
||||
M: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
|
||||
M: Jason Cooper <jason@lakedaemon.net>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
|
|
|||
12
Makefile
12
Makefile
|
|
@ -2,7 +2,7 @@
|
|||
VERSION = 5
|
||||
PATCHLEVEL = 10
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc6
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Kleptomaniac Octopus
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
@ -826,7 +826,9 @@ else
|
|||
DEBUG_CFLAGS += -g
|
||||
endif
|
||||
|
||||
ifneq ($(LLVM_IAS),1)
|
||||
KBUILD_AFLAGS += -Wa,-gdwarf-2
|
||||
endif
|
||||
|
||||
ifdef CONFIG_DEBUG_INFO_DWARF4
|
||||
DEBUG_CFLAGS += -gdwarf-4
|
||||
|
|
@ -944,7 +946,7 @@ KBUILD_CFLAGS += $(call cc-option,-Werror=incompatible-pointer-types)
|
|||
KBUILD_CFLAGS += $(call cc-option,-Werror=designated-init)
|
||||
|
||||
# change __FILE__ to the relative path from the srctree
|
||||
KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
|
||||
KBUILD_CPPFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
|
||||
|
||||
# ensure -fcf-protection is disabled when using retpoline as it is
|
||||
# incompatible with -mindirect-branch=thunk-extern
|
||||
|
|
@ -982,6 +984,12 @@ ifeq ($(CONFIG_RELR),y)
|
|||
LDFLAGS_vmlinux += --pack-dyn-relocs=relr
|
||||
endif
|
||||
|
||||
# We never want expected sections to be placed heuristically by the
|
||||
# linker. All sections should be explicitly named in the linker script.
|
||||
ifdef CONFIG_LD_ORPHAN_WARN
|
||||
LDFLAGS_vmlinux += --orphan-handling=warn
|
||||
endif
|
||||
|
||||
# Align the bit size of userspace programs with the kernel
|
||||
KBUILD_USERCFLAGS += $(filter -m32 -m64 --target=%, $(KBUILD_CFLAGS))
|
||||
KBUILD_USERLDFLAGS += $(filter -m32 -m64 --target=%, $(KBUILD_CFLAGS))
|
||||
|
|
|
|||
|
|
@ -1028,6 +1028,15 @@ config HAVE_STATIC_CALL_INLINE
|
|||
bool
|
||||
depends on HAVE_STATIC_CALL
|
||||
|
||||
config ARCH_WANT_LD_ORPHAN_WARN
|
||||
bool
|
||||
help
|
||||
An arch should select this symbol once all linker sections are explicitly
|
||||
included, size-asserted, or discarded in the linker scripts. This is
|
||||
important because we never want expected sections to be placed heuristically
|
||||
by the linker, since the locations of such sections can change between linker
|
||||
versions.
|
||||
|
||||
source "kernel/gcov/Kconfig"
|
||||
|
||||
source "scripts/gcc-plugins/Kconfig"
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ config ARM
|
|||
select ARCH_USE_CMPXCHG_LOCKREF
|
||||
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
|
||||
select ARCH_WANT_IPC_PARSE_VERSION
|
||||
select ARCH_WANT_LD_ORPHAN_WARN
|
||||
select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
|
||||
select BUILDTIME_TABLE_SORT if MMU
|
||||
select CLONE_BACKWARDS
|
||||
|
|
|
|||
|
|
@ -16,10 +16,6 @@ LDFLAGS_vmlinux += --be8
|
|||
KBUILD_LDFLAGS_MODULE += --be8
|
||||
endif
|
||||
|
||||
# We never want expected sections to be placed heuristically by the
|
||||
# linker. All sections should be explicitly named in the linker script.
|
||||
LDFLAGS_vmlinux += $(call ld-option, --orphan-handling=warn)
|
||||
|
||||
GZFLAGS :=-9
|
||||
#KBUILD_CFLAGS +=-pipe
|
||||
|
||||
|
|
|
|||
|
|
@ -129,7 +129,9 @@ LDFLAGS_vmlinux += --no-undefined
|
|||
# Delete all temporary local symbols
|
||||
LDFLAGS_vmlinux += -X
|
||||
# Report orphan sections
|
||||
LDFLAGS_vmlinux += $(call ld-option, --orphan-handling=warn)
|
||||
ifdef CONFIG_LD_ORPHAN_WARN
|
||||
LDFLAGS_vmlinux += --orphan-handling=warn
|
||||
endif
|
||||
# Next argument is a linker script
|
||||
LDFLAGS_vmlinux += -T
|
||||
|
||||
|
|
|
|||
|
|
@ -551,7 +551,7 @@
|
|||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -166,7 +166,6 @@
|
|||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -223,8 +223,7 @@
|
|||
};
|
||||
|
||||
&ssp3 {
|
||||
/delete-property/ #address-cells;
|
||||
/delete-property/ #size-cells;
|
||||
#address-cells = <0>;
|
||||
spi-slave;
|
||||
status = "okay";
|
||||
ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>;
|
||||
|
|
|
|||
|
|
@ -132,7 +132,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_rgmii_pins>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-supply = <®_gmac_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2015 Adam Sampson <ats@offog.org>
|
||||
* Copyright 2015-2020 Adam Sampson <ats@offog.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
|
|
@ -115,7 +115,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_rgmii_pins>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
|
||||
/ {
|
||||
model = "PineCube IP Camera";
|
||||
compatible = "pine64,pinecube", "allwinner,sun8i-s3";
|
||||
compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart2;
|
||||
|
|
|
|||
|
|
@ -539,7 +539,7 @@
|
|||
gic: interrupt-controller@1c81000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x01c81000 0x1000>,
|
||||
<0x01c82000 0x1000>,
|
||||
<0x01c82000 0x2000>,
|
||||
<0x01c84000 0x2000>,
|
||||
<0x01c86000 0x2000>;
|
||||
interrupt-controller;
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_rgmii_pins>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-supply = <®_dc1sw>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -198,16 +198,16 @@
|
|||
};
|
||||
|
||||
®_dc1sw {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc-gmac-phy";
|
||||
};
|
||||
|
||||
®_dcdc1 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc-3v0";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc-3v3";
|
||||
};
|
||||
|
||||
®_dcdc2 {
|
||||
|
|
|
|||
|
|
@ -81,7 +81,6 @@ CONFIG_PARTITION_ADVANCED=y
|
|||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_ZSMALLOC=m
|
||||
CONFIG_ZSMALLOC_PGTABLE_MAPPING=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ void __init imx_init_revision_from_anatop(void)
|
|||
|
||||
src_np = of_find_compatible_node(NULL, NULL,
|
||||
"fsl,imx6ul-src");
|
||||
src_base = of_iomap(np, 0);
|
||||
src_base = of_iomap(src_np, 0);
|
||||
of_node_put(src_np);
|
||||
WARN_ON(!src_base);
|
||||
sbmr2 = readl_relaxed(src_base + SRC_SBMR2);
|
||||
|
|
|
|||
|
|
@ -6,9 +6,6 @@
|
|||
#ifndef __MEMORY_H
|
||||
#define __MEMORY_H
|
||||
|
||||
#define MAX_PHYSMEM_BITS 36
|
||||
#define SECTION_SIZE_BITS 34
|
||||
|
||||
#define KEYSTONE_LOW_PHYS_START 0x80000000ULL
|
||||
#define KEYSTONE_LOW_PHYS_SIZE 0x80000000ULL /* 2G */
|
||||
#define KEYSTONE_LOW_PHYS_END (KEYSTONE_LOW_PHYS_START + \
|
||||
|
|
|
|||
|
|
@ -288,7 +288,7 @@ static struct gpiod_lookup_table osk_usb_gpio_table = {
|
|||
.dev_id = "ohci",
|
||||
.table = {
|
||||
/* Power GPIO on the I2C-attached TPS65010 */
|
||||
GPIO_LOOKUP("i2c-tps65010", 1, "power", GPIO_ACTIVE_HIGH),
|
||||
GPIO_LOOKUP("tps65010", 0, "power", GPIO_ACTIVE_HIGH),
|
||||
GPIO_LOOKUP(OMAP_GPIO_LABEL, 9, "overcurrent",
|
||||
GPIO_ACTIVE_HIGH),
|
||||
},
|
||||
|
|
|
|||
|
|
@ -66,6 +66,7 @@ static const char * const sun8i_board_dt_compat[] = {
|
|||
"allwinner,sun8i-h2-plus",
|
||||
"allwinner,sun8i-h3",
|
||||
"allwinner,sun8i-r40",
|
||||
"allwinner,sun8i-v3",
|
||||
"allwinner,sun8i-v3s",
|
||||
NULL,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -81,6 +81,7 @@ config ARM64
|
|||
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
|
||||
select ARCH_WANT_FRAME_POINTERS
|
||||
select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
|
||||
select ARCH_WANT_LD_ORPHAN_WARN
|
||||
select ARCH_HAS_UBSAN_SANITIZE_ALL
|
||||
select ARM_AMBA
|
||||
select ARM_ARCH_TIMER
|
||||
|
|
|
|||
|
|
@ -28,10 +28,6 @@ LDFLAGS_vmlinux += --fix-cortex-a53-843419
|
|||
endif
|
||||
endif
|
||||
|
||||
# We never want expected sections to be placed heuristically by the
|
||||
# linker. All sections should be explicitly named in the linker script.
|
||||
LDFLAGS_vmlinux += $(call ld-option, --orphan-handling=warn)
|
||||
|
||||
ifeq ($(CONFIG_ARM64_USE_LSE_ATOMICS), y)
|
||||
ifneq ($(CONFIG_ARM64_LSE_ATOMICS), y)
|
||||
$(warning LSE atomics not supported by binutils)
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@
|
|||
&emac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&ext_rgmii_phy>;
|
||||
phy-supply = <®_dc1sw>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@
|
|||
pinctrl-0 = <&emac_rgmii_pins>;
|
||||
phy-supply = <®_gmac_3v3>;
|
||||
phy-handle = <&ext_rgmii_phy>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
&emac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ext_rgmii_pins>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&ext_rgmii_phy>;
|
||||
phy-supply = <®_gmac_3v3>;
|
||||
allwinner,rx-delay-ps = <200>;
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ config PPC
|
|||
select ARCH_USE_QUEUED_SPINLOCKS if PPC_QUEUED_SPINLOCKS
|
||||
select ARCH_WANT_IPC_PARSE_VERSION
|
||||
select ARCH_WANT_IRQS_OFF_ACTIVATE_MM
|
||||
select ARCH_WANT_LD_ORPHAN_WARN
|
||||
select ARCH_WEAK_RELEASE_ACQUIRE
|
||||
select BINFMT_ELF
|
||||
select BUILDTIME_TABLE_SORT
|
||||
|
|
|
|||
|
|
@ -123,7 +123,6 @@ endif
|
|||
LDFLAGS_vmlinux-y := -Bstatic
|
||||
LDFLAGS_vmlinux-$(CONFIG_RELOCATABLE) := -pie
|
||||
LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-y)
|
||||
LDFLAGS_vmlinux += $(call ld-option,--orphan-handling=warn)
|
||||
|
||||
ifdef CONFIG_PPC64
|
||||
ifeq ($(call cc-option-yn,-mcmodel=medium),y)
|
||||
|
|
|
|||
|
|
@ -242,6 +242,18 @@ extern void radix_init_pseries(void);
|
|||
static inline void radix_init_pseries(void) { };
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
#define arch_clear_mm_cpumask_cpu(cpu, mm) \
|
||||
do { \
|
||||
if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { \
|
||||
atomic_dec(&(mm)->context.active_cpus); \
|
||||
cpumask_clear_cpu(cpu, mm_cpumask(mm)); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
void cleanup_cpu_mmu_context(void);
|
||||
#endif
|
||||
|
||||
static inline int get_user_context(mm_context_t *ctx, unsigned long ea)
|
||||
{
|
||||
int index = ea >> MAX_EA_BITS_PER_CONTEXT;
|
||||
|
|
|
|||
|
|
@ -1214,12 +1214,9 @@ void kvmppc_xive_cleanup_vcpu(struct kvm_vcpu *vcpu)
|
|||
static bool kvmppc_xive_vcpu_id_valid(struct kvmppc_xive *xive, u32 cpu)
|
||||
{
|
||||
/* We have a block of xive->nr_servers VPs. We just need to check
|
||||
* raw vCPU ids are below the expected limit for this guest's
|
||||
* core stride ; kvmppc_pack_vcpu_id() will pack them down to an
|
||||
* index that can be safely used to compute a VP id that belongs
|
||||
* to the VP block.
|
||||
* packed vCPU ids are below that.
|
||||
*/
|
||||
return cpu < xive->nr_servers * xive->kvm->arch.emul_smt_mode;
|
||||
return kvmppc_pack_vcpu_id(xive->kvm, cpu) < xive->nr_servers;
|
||||
}
|
||||
|
||||
int kvmppc_xive_compute_vp_id(struct kvmppc_xive *xive, u32 cpu, u32 *vp)
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
|
||||
ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
|
||||
|
||||
obj-y := fault.o mem.o pgtable.o mmap.o \
|
||||
obj-y := fault.o mem.o pgtable.o mmap.o maccess.o \
|
||||
init_$(BITS).o pgtable_$(BITS).o \
|
||||
pgtable-frag.o ioremap.o ioremap_$(BITS).o \
|
||||
init-common.o mmu_context.o drmem.o
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ static __always_inline void tlbiel_hash_set_isa300(unsigned int set, unsigned in
|
|||
rs = ((unsigned long)pid << PPC_BITLSHIFT(31));
|
||||
|
||||
asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4)
|
||||
: : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "r"(r)
|
||||
: : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
|
|
@ -92,16 +92,15 @@ static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is)
|
|||
asm volatile("ptesync": : :"memory");
|
||||
|
||||
/*
|
||||
* Flush the first set of the TLB, and any caching of partition table
|
||||
* entries. Then flush the remaining sets of the TLB. Hash mode uses
|
||||
* partition scoped TLB translations.
|
||||
* Flush the partition table cache if this is HV mode.
|
||||
*/
|
||||
tlbiel_hash_set_isa300(0, is, 0, 2, 0);
|
||||
for (set = 1; set < num_sets; set++)
|
||||
tlbiel_hash_set_isa300(set, is, 0, 0, 0);
|
||||
if (early_cpu_has_feature(CPU_FTR_HVMODE))
|
||||
tlbiel_hash_set_isa300(0, is, 0, 2, 0);
|
||||
|
||||
/*
|
||||
* Now invalidate the process table cache.
|
||||
* Now invalidate the process table cache. UPRT=0 HPT modes (what
|
||||
* current hardware implements) do not use the process table, but
|
||||
* add the flushes anyway.
|
||||
*
|
||||
* From ISA v3.0B p. 1078:
|
||||
* The following forms are invalid.
|
||||
|
|
@ -110,6 +109,14 @@ static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is)
|
|||
*/
|
||||
tlbiel_hash_set_isa300(0, is, 0, 2, 1);
|
||||
|
||||
/*
|
||||
* Then flush the sets of the TLB proper. Hash mode uses
|
||||
* partition scoped TLB translations, which may be flushed
|
||||
* in !HV mode.
|
||||
*/
|
||||
for (set = 0; set < num_sets; set++)
|
||||
tlbiel_hash_set_isa300(set, is, 0, 0, 0);
|
||||
|
||||
ppc_after_tlbiel_barrier();
|
||||
|
||||
asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT "; isync" : : :"memory");
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/export.h>
|
||||
#include <linux/gfp.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/cpu.h>
|
||||
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/pgalloc.h>
|
||||
|
|
@ -307,3 +308,22 @@ void radix__switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
|
|||
isync();
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* cleanup_cpu_mmu_context - Clean up MMU details for this CPU (newly offlined)
|
||||
*
|
||||
* This clears the CPU from mm_cpumask for all processes, and then flushes the
|
||||
* local TLB to ensure TLB coherency in case the CPU is onlined again.
|
||||
*
|
||||
* KVM guest translations are not necessarily flushed here. If KVM started
|
||||
* using mm_cpumask or the Linux APIs which do, this would have to be resolved.
|
||||
*/
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
void cleanup_cpu_mmu_context(void)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
clear_tasks_mm_cpumask(cpu);
|
||||
tlbiel_all();
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,9 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size)
|
||||
{
|
||||
return is_kernel_addr((unsigned long)unsafe_src);
|
||||
}
|
||||
|
|
@ -742,8 +742,7 @@ static int __init parse_numa_properties(void)
|
|||
of_node_put(cpu);
|
||||
}
|
||||
|
||||
if (likely(nid > 0))
|
||||
node_set_online(nid);
|
||||
node_set_online(nid);
|
||||
}
|
||||
|
||||
get_n_mem_cells(&n_mem_addr_cells, &n_mem_size_cells);
|
||||
|
|
|
|||
|
|
@ -911,6 +911,8 @@ static int smp_core99_cpu_disable(void)
|
|||
|
||||
mpic_cpu_set_priority(0xf);
|
||||
|
||||
cleanup_cpu_mmu_context();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -211,11 +211,16 @@ static void __init pnv_init(void)
|
|||
add_preferred_console("hvc", 0, NULL);
|
||||
|
||||
if (!radix_enabled()) {
|
||||
size_t size = sizeof(struct slb_entry) * mmu_slb_size;
|
||||
int i;
|
||||
|
||||
/* Allocate per cpu area to save old slb contents during MCE */
|
||||
for_each_possible_cpu(i)
|
||||
paca_ptrs[i]->mce_faulty_slbs = memblock_alloc_node(mmu_slb_size, __alignof__(*paca_ptrs[i]->mce_faulty_slbs), cpu_to_node(i));
|
||||
for_each_possible_cpu(i) {
|
||||
paca_ptrs[i]->mce_faulty_slbs =
|
||||
memblock_alloc_node(size,
|
||||
__alignof__(struct slb_entry),
|
||||
cpu_to_node(i));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -143,6 +143,9 @@ static int pnv_smp_cpu_disable(void)
|
|||
xive_smp_disable_cpu();
|
||||
else
|
||||
xics_migrate_irqs_away();
|
||||
|
||||
cleanup_cpu_mmu_context();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -90,6 +90,9 @@ static int pseries_cpu_disable(void)
|
|||
xive_smp_disable_cpu();
|
||||
else
|
||||
xics_migrate_irqs_away();
|
||||
|
||||
cleanup_cpu_mmu_context();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -458,7 +458,8 @@ again:
|
|||
return hwirq;
|
||||
}
|
||||
|
||||
virq = irq_create_mapping(NULL, hwirq);
|
||||
virq = irq_create_mapping_affinity(NULL, hwirq,
|
||||
entry->affinity);
|
||||
|
||||
if (!virq) {
|
||||
pr_debug("rtas_msi: Failed mapping hwirq %d\n", hwirq);
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@
|
|||
FUNC_NAME: /* %o0=src, %o1=dst, %o2=len */
|
||||
LOAD(prefetch, %o0 + 0x000, #n_reads)
|
||||
xor %o0, %o1, %g1
|
||||
mov 1, %o3
|
||||
mov -1, %o3
|
||||
clr %o4
|
||||
andcc %g1, 0x3, %g0
|
||||
bne,pn %icc, 95f
|
||||
|
|
|
|||
|
|
@ -100,6 +100,7 @@ config X86
|
|||
select ARCH_WANT_DEFAULT_BPF_JIT if X86_64
|
||||
select ARCH_WANTS_DYNAMIC_TASK_STRUCT
|
||||
select ARCH_WANT_HUGE_PMD_SHARE
|
||||
select ARCH_WANT_LD_ORPHAN_WARN
|
||||
select ARCH_WANTS_THP_SWAP if X86_64
|
||||
select BUILDTIME_TABLE_SORT
|
||||
select CLKEVT_I8253
|
||||
|
|
|
|||
|
|
@ -209,9 +209,6 @@ ifdef CONFIG_X86_64
|
|||
LDFLAGS_vmlinux += -z max-page-size=0x200000
|
||||
endif
|
||||
|
||||
# We never want expected sections to be placed heuristically by the
|
||||
# linker. All sections should be explicitly named in the linker script.
|
||||
LDFLAGS_vmlinux += $(call ld-option, --orphan-handling=warn)
|
||||
|
||||
archscripts: scripts_basic
|
||||
$(Q)$(MAKE) $(build)=arch/x86/tools relocs
|
||||
|
|
|
|||
|
|
@ -61,7 +61,9 @@ KBUILD_LDFLAGS += $(call ld-option,--no-ld-generated-unwind-info)
|
|||
# Compressed kernel should be built as PIE since it may be loaded at any
|
||||
# address by the bootloader.
|
||||
LDFLAGS_vmlinux := -pie $(call ld-option, --no-dynamic-linker)
|
||||
LDFLAGS_vmlinux += $(call ld-option, --orphan-handling=warn)
|
||||
ifdef CONFIG_LD_ORPHAN_WARN
|
||||
LDFLAGS_vmlinux += --orphan-handling=warn
|
||||
endif
|
||||
LDFLAGS_vmlinux += -T
|
||||
|
||||
hostprogs := mkpiggy
|
||||
|
|
|
|||
|
|
@ -32,13 +32,12 @@ struct ghcb *boot_ghcb;
|
|||
*/
|
||||
static bool insn_has_rep_prefix(struct insn *insn)
|
||||
{
|
||||
insn_byte_t p;
|
||||
int i;
|
||||
|
||||
insn_get_prefixes(insn);
|
||||
|
||||
for (i = 0; i < insn->prefixes.nbytes; i++) {
|
||||
insn_byte_t p = insn->prefixes.bytes[i];
|
||||
|
||||
for_each_insn_prefix(insn, i, p) {
|
||||
if (p == 0xf2 || p == 0xf3)
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1916,7 +1916,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
|
|||
* that caused the PEBS record. It's called collision.
|
||||
* If collision happened, the record will be dropped.
|
||||
*/
|
||||
if (p->status != (1ULL << bit)) {
|
||||
if (pebs_status != (1ULL << bit)) {
|
||||
for_each_set_bit(i, (unsigned long *)&pebs_status, size)
|
||||
error[i]++;
|
||||
continue;
|
||||
|
|
@ -1940,7 +1940,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
|
|||
if (error[bit]) {
|
||||
perf_log_lost_samples(event, error[bit]);
|
||||
|
||||
if (perf_event_account_interrupt(event))
|
||||
if (iregs && perf_event_account_interrupt(event))
|
||||
x86_pmu_stop(event, 0);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -201,6 +201,21 @@ static inline int insn_offset_immediate(struct insn *insn)
|
|||
return insn_offset_displacement(insn) + insn->displacement.nbytes;
|
||||
}
|
||||
|
||||
/**
|
||||
* for_each_insn_prefix() -- Iterate prefixes in the instruction
|
||||
* @insn: Pointer to struct insn.
|
||||
* @idx: Index storage.
|
||||
* @prefix: Prefix byte.
|
||||
*
|
||||
* Iterate prefix bytes of given @insn. Each prefix byte is stored in @prefix
|
||||
* and the index is stored in @idx (note that this @idx is just for a cursor,
|
||||
* do not change it.)
|
||||
* Since prefixes.nbytes can be bigger than 4 if some prefixes
|
||||
* are repeated, it cannot be used for looping over the prefixes.
|
||||
*/
|
||||
#define for_each_insn_prefix(insn, idx, prefix) \
|
||||
for (idx = 0; idx < ARRAY_SIZE(insn->prefixes.bytes) && (prefix = insn->prefixes.bytes[idx]) != 0; idx++)
|
||||
|
||||
#define POP_SS_OPCODE 0x1f
|
||||
#define MOV_SREG_OPCODE 0x8e
|
||||
|
||||
|
|
|
|||
|
|
@ -161,7 +161,7 @@ static int __init early_set_hub_type(void)
|
|||
/* UV4/4A only have a revision difference */
|
||||
case UV4_HUB_PART_NUMBER:
|
||||
uv_min_hub_revision_id = node_id.s.revision
|
||||
+ UV4_HUB_REVISION_BASE;
|
||||
+ UV4_HUB_REVISION_BASE - 1;
|
||||
uv_hub_type_set(UV4);
|
||||
if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE)
|
||||
uv_hub_type_set(UV4|UV4A);
|
||||
|
|
|
|||
|
|
@ -570,6 +570,8 @@ static void domain_add_cpu(int cpu, struct rdt_resource *r)
|
|||
|
||||
if (d) {
|
||||
cpumask_set_cpu(cpu, &d->cpu_mask);
|
||||
if (r->cache.arch_has_per_cpu_cfg)
|
||||
rdt_domain_reconfigure_cdp(r);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -923,6 +925,7 @@ static __init void rdt_init_res_defs_intel(void)
|
|||
r->rid == RDT_RESOURCE_L2CODE) {
|
||||
r->cache.arch_has_sparse_bitmaps = false;
|
||||
r->cache.arch_has_empty_bitmaps = false;
|
||||
r->cache.arch_has_per_cpu_cfg = false;
|
||||
} else if (r->rid == RDT_RESOURCE_MBA) {
|
||||
r->msr_base = MSR_IA32_MBA_THRTL_BASE;
|
||||
r->msr_update = mba_wrmsr_intel;
|
||||
|
|
@ -943,6 +946,7 @@ static __init void rdt_init_res_defs_amd(void)
|
|||
r->rid == RDT_RESOURCE_L2CODE) {
|
||||
r->cache.arch_has_sparse_bitmaps = true;
|
||||
r->cache.arch_has_empty_bitmaps = true;
|
||||
r->cache.arch_has_per_cpu_cfg = true;
|
||||
} else if (r->rid == RDT_RESOURCE_MBA) {
|
||||
r->msr_base = MSR_IA32_MBA_BW_BASE;
|
||||
r->msr_update = mba_wrmsr_amd;
|
||||
|
|
|
|||
|
|
@ -360,6 +360,8 @@ struct msr_param {
|
|||
* executing entities
|
||||
* @arch_has_sparse_bitmaps: True if a bitmap like f00f is valid.
|
||||
* @arch_has_empty_bitmaps: True if the '0' bitmap is valid.
|
||||
* @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache
|
||||
* level has CPU scope.
|
||||
*/
|
||||
struct rdt_cache {
|
||||
unsigned int cbm_len;
|
||||
|
|
@ -369,6 +371,7 @@ struct rdt_cache {
|
|||
unsigned int shareable_bits;
|
||||
bool arch_has_sparse_bitmaps;
|
||||
bool arch_has_empty_bitmaps;
|
||||
bool arch_has_per_cpu_cfg;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -1909,8 +1909,13 @@ static int set_cache_qos_cfg(int level, bool enable)
|
|||
|
||||
r_l = &rdt_resources_all[level];
|
||||
list_for_each_entry(d, &r_l->domains, list) {
|
||||
/* Pick one CPU from each domain instance to update MSR */
|
||||
cpumask_set_cpu(cpumask_any(&d->cpu_mask), cpu_mask);
|
||||
if (r_l->cache.arch_has_per_cpu_cfg)
|
||||
/* Pick all the CPUs in the domain instance */
|
||||
for_each_cpu(cpu, &d->cpu_mask)
|
||||
cpumask_set_cpu(cpu, cpu_mask);
|
||||
else
|
||||
/* Pick one CPU from each domain instance to update MSR */
|
||||
cpumask_set_cpu(cpumask_any(&d->cpu_mask), cpu_mask);
|
||||
}
|
||||
cpu = get_cpu();
|
||||
/* Update QOS_CFG MSR on this cpu if it's in cpu_mask. */
|
||||
|
|
|
|||
|
|
@ -255,12 +255,13 @@ static volatile u32 good_2byte_insns[256 / 32] = {
|
|||
|
||||
static bool is_prefix_bad(struct insn *insn)
|
||||
{
|
||||
insn_byte_t p;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < insn->prefixes.nbytes; i++) {
|
||||
for_each_insn_prefix(insn, i, p) {
|
||||
insn_attr_t attr;
|
||||
|
||||
attr = inat_get_opcode_attribute(insn->prefixes.bytes[i]);
|
||||
attr = inat_get_opcode_attribute(p);
|
||||
switch (attr) {
|
||||
case INAT_MAKE_PREFIX(INAT_PFX_ES):
|
||||
case INAT_MAKE_PREFIX(INAT_PFX_CS):
|
||||
|
|
@ -715,6 +716,7 @@ static const struct uprobe_xol_ops push_xol_ops = {
|
|||
static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
|
||||
{
|
||||
u8 opc1 = OPCODE1(insn);
|
||||
insn_byte_t p;
|
||||
int i;
|
||||
|
||||
switch (opc1) {
|
||||
|
|
@ -746,8 +748,8 @@ static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
|
|||
* Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix.
|
||||
* No one uses these insns, reject any branch insns with such prefix.
|
||||
*/
|
||||
for (i = 0; i < insn->prefixes.nbytes; i++) {
|
||||
if (insn->prefixes.bytes[i] == 0x66)
|
||||
for_each_insn_prefix(insn, i, p) {
|
||||
if (p == 0x66)
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -63,13 +63,12 @@ static bool is_string_insn(struct insn *insn)
|
|||
*/
|
||||
bool insn_has_rep_prefix(struct insn *insn)
|
||||
{
|
||||
insn_byte_t p;
|
||||
int i;
|
||||
|
||||
insn_get_prefixes(insn);
|
||||
|
||||
for (i = 0; i < insn->prefixes.nbytes; i++) {
|
||||
insn_byte_t p = insn->prefixes.bytes[i];
|
||||
|
||||
for_each_insn_prefix(insn, i, p) {
|
||||
if (p == 0xf2 || p == 0xf3)
|
||||
return true;
|
||||
}
|
||||
|
|
@ -95,14 +94,15 @@ static int get_seg_reg_override_idx(struct insn *insn)
|
|||
{
|
||||
int idx = INAT_SEG_REG_DEFAULT;
|
||||
int num_overrides = 0, i;
|
||||
insn_byte_t p;
|
||||
|
||||
insn_get_prefixes(insn);
|
||||
|
||||
/* Look for any segment override prefixes. */
|
||||
for (i = 0; i < insn->prefixes.nbytes; i++) {
|
||||
for_each_insn_prefix(insn, i, p) {
|
||||
insn_attr_t attr;
|
||||
|
||||
attr = inat_get_opcode_attribute(insn->prefixes.bytes[i]);
|
||||
attr = inat_get_opcode_attribute(p);
|
||||
switch (attr) {
|
||||
case INAT_MAKE_PREFIX(INAT_PFX_CS):
|
||||
idx = INAT_SEG_REG_CS;
|
||||
|
|
|
|||
|
|
@ -144,7 +144,7 @@ static struct bio *blk_bio_write_same_split(struct request_queue *q,
|
|||
static inline unsigned get_max_io_size(struct request_queue *q,
|
||||
struct bio *bio)
|
||||
{
|
||||
unsigned sectors = blk_max_size_offset(q, bio->bi_iter.bi_sector);
|
||||
unsigned sectors = blk_max_size_offset(q, bio->bi_iter.bi_sector, 0);
|
||||
unsigned max_sectors = sectors;
|
||||
unsigned pbs = queue_physical_block_size(q) >> SECTOR_SHIFT;
|
||||
unsigned lbs = queue_logical_block_size(q) >> SECTOR_SHIFT;
|
||||
|
|
|
|||
|
|
@ -547,7 +547,10 @@ int blk_stack_limits(struct queue_limits *t, struct queue_limits *b,
|
|||
|
||||
t->io_min = max(t->io_min, b->io_min);
|
||||
t->io_opt = lcm_not_zero(t->io_opt, b->io_opt);
|
||||
t->chunk_sectors = lcm_not_zero(t->chunk_sectors, b->chunk_sectors);
|
||||
|
||||
/* Set non-power-of-2 compatible chunk_sectors boundary */
|
||||
if (b->chunk_sectors)
|
||||
t->chunk_sectors = gcd(t->chunk_sectors, b->chunk_sectors);
|
||||
|
||||
/* Physical block size a multiple of the logical block size? */
|
||||
if (t->physical_block_size & (t->logical_block_size - 1)) {
|
||||
|
|
|
|||
|
|
@ -47,27 +47,20 @@ static int spk_ttyio_ldisc_open(struct tty_struct *tty)
|
|||
{
|
||||
struct spk_ldisc_data *ldisc_data;
|
||||
|
||||
if (tty != speakup_tty)
|
||||
/* Somebody tried to use this line discipline outside speakup */
|
||||
return -ENODEV;
|
||||
|
||||
if (!tty->ops->write)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
mutex_lock(&speakup_tty_mutex);
|
||||
if (speakup_tty) {
|
||||
mutex_unlock(&speakup_tty_mutex);
|
||||
return -EBUSY;
|
||||
}
|
||||
speakup_tty = tty;
|
||||
|
||||
ldisc_data = kmalloc(sizeof(*ldisc_data), GFP_KERNEL);
|
||||
if (!ldisc_data) {
|
||||
speakup_tty = NULL;
|
||||
mutex_unlock(&speakup_tty_mutex);
|
||||
if (!ldisc_data)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
init_completion(&ldisc_data->completion);
|
||||
ldisc_data->buf_free = true;
|
||||
speakup_tty->disc_data = ldisc_data;
|
||||
mutex_unlock(&speakup_tty_mutex);
|
||||
tty->disc_data = ldisc_data;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -191,9 +184,25 @@ static int spk_ttyio_initialise_ldisc(struct spk_synth *synth)
|
|||
|
||||
tty_unlock(tty);
|
||||
|
||||
mutex_lock(&speakup_tty_mutex);
|
||||
speakup_tty = tty;
|
||||
ret = tty_set_ldisc(tty, N_SPEAKUP);
|
||||
if (ret)
|
||||
pr_err("speakup: Failed to set N_SPEAKUP on tty\n");
|
||||
speakup_tty = NULL;
|
||||
mutex_unlock(&speakup_tty_mutex);
|
||||
|
||||
if (!ret)
|
||||
/* Success */
|
||||
return 0;
|
||||
|
||||
pr_err("speakup: Failed to set N_SPEAKUP on tty\n");
|
||||
|
||||
tty_lock(tty);
|
||||
if (tty->ops->close)
|
||||
tty->ops->close(tty, NULL);
|
||||
tty_unlock(tty);
|
||||
|
||||
tty_kclose(tty);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ config MXC_CLK
|
|||
depends on ARCH_MXC || COMPILE_TEST
|
||||
|
||||
config MXC_CLK_SCU
|
||||
tristate "IMX SCU clock"
|
||||
depends on ARCH_MXC || COMPILE_TEST
|
||||
tristate
|
||||
depends on ARCH_MXC
|
||||
depends on IMX_SCU && HAVE_ARM_SMCCC
|
||||
|
||||
config CLK_IMX1
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ struct r9a06g032_clkdesc {
|
|||
u16 sel, g1, r1, g2, r2;
|
||||
} dual;
|
||||
};
|
||||
} __packed;
|
||||
};
|
||||
|
||||
#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
|
||||
{ .gate = _clk, .reset = _rst, \
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
#define PM_API_FEATURE_CHECK_MAX_ORDER 7
|
||||
|
||||
static bool feature_check_enabled;
|
||||
DEFINE_HASHTABLE(pm_api_features_map, PM_API_FEATURE_CHECK_MAX_ORDER);
|
||||
static DEFINE_HASHTABLE(pm_api_features_map, PM_API_FEATURE_CHECK_MAX_ORDER);
|
||||
|
||||
/**
|
||||
* struct pm_api_feature_data - PM API Feature data
|
||||
|
|
|
|||
|
|
@ -142,6 +142,7 @@ config FPGA_DFL
|
|||
tristate "FPGA Device Feature List (DFL) support"
|
||||
select FPGA_BRIDGE
|
||||
select FPGA_REGION
|
||||
depends on HAS_IOMEM
|
||||
help
|
||||
Device Feature List (DFL) defines a feature list structure that
|
||||
creates a linked list of feature headers within the MMIO space
|
||||
|
|
|
|||
|
|
@ -192,6 +192,7 @@ static int arizona_gpio_probe(struct platform_device *pdev)
|
|||
ret = devm_gpiochip_add_data(&pdev->dev, &arizona_gpio->gpio_chip,
|
||||
arizona_gpio);
|
||||
if (ret < 0) {
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
dev_err(&pdev->dev, "Could not register gpiochip, %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -724,6 +724,8 @@ static int dwapb_gpio_probe(struct platform_device *pdev)
|
|||
return err;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, gpio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -598,7 +598,7 @@ static int sprd_eic_probe(struct platform_device *pdev)
|
|||
*/
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||
if (!res)
|
||||
continue;
|
||||
break;
|
||||
|
||||
sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(sprd_eic->base[i]))
|
||||
|
|
|
|||
|
|
@ -1197,6 +1197,13 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
|
|||
|
||||
devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
|
||||
|
||||
/* Some MVEBU SoCs have simple PWM support for GPIO lines */
|
||||
if (IS_ENABLED(CONFIG_PWM)) {
|
||||
err = mvebu_pwm_probe(pdev, mvchip, id);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Some gpio controllers do not provide irq support */
|
||||
if (!have_irqs)
|
||||
return 0;
|
||||
|
|
@ -1206,7 +1213,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
|
|||
if (!mvchip->domain) {
|
||||
dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
|
||||
mvchip->chip.label);
|
||||
return -ENODEV;
|
||||
err = -ENODEV;
|
||||
goto err_pwm;
|
||||
}
|
||||
|
||||
err = irq_alloc_domain_generic_chips(
|
||||
|
|
@ -1254,14 +1262,12 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
|
|||
mvchip);
|
||||
}
|
||||
|
||||
/* Some MVEBU SoCs have simple PWM support for GPIO lines */
|
||||
if (IS_ENABLED(CONFIG_PWM))
|
||||
return mvebu_pwm_probe(pdev, mvchip, id);
|
||||
|
||||
return 0;
|
||||
|
||||
err_domain:
|
||||
irq_domain_remove(mvchip->domain);
|
||||
err_pwm:
|
||||
pwmchip_remove(&mvchip->mvpwm->chip);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -574,7 +574,7 @@ static int zynq_gpio_irq_reqres(struct irq_data *d)
|
|||
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
|
||||
int ret;
|
||||
|
||||
ret = pm_runtime_get_sync(chip->parent);
|
||||
ret = pm_runtime_resume_and_get(chip->parent);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
@ -942,7 +942,7 @@ static int zynq_gpio_probe(struct platform_device *pdev)
|
|||
|
||||
pm_runtime_set_active(&pdev->dev);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
ret = pm_runtime_get_sync(&pdev->dev);
|
||||
ret = pm_runtime_resume_and_get(&pdev->dev);
|
||||
if (ret < 0)
|
||||
goto err_pm_dis;
|
||||
|
||||
|
|
|
|||
|
|
@ -1806,6 +1806,11 @@ EXPORT_SYMBOL_GPL(gpiochip_generic_request);
|
|||
*/
|
||||
void gpiochip_generic_free(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
#ifdef CONFIG_PINCTRL
|
||||
if (list_empty(&gc->gpiodev->pin_ranges))
|
||||
return;
|
||||
#endif
|
||||
|
||||
pinctrl_gpio_free(gc->gpiodev->base + offset);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(gpiochip_generic_free);
|
||||
|
|
|
|||
|
|
@ -459,6 +459,7 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
|
|||
struct amdgpu_device *adev = drm_to_adev(dev);
|
||||
struct amdgpu_bo *bo;
|
||||
struct amdgpu_bo_param bp;
|
||||
struct drm_gem_object *gobj;
|
||||
int ret;
|
||||
|
||||
memset(&bp, 0, sizeof(bp));
|
||||
|
|
@ -469,17 +470,20 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
|
|||
bp.type = ttm_bo_type_sg;
|
||||
bp.resv = resv;
|
||||
dma_resv_lock(resv, NULL);
|
||||
ret = amdgpu_bo_create(adev, &bp, &bo);
|
||||
ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
|
||||
AMDGPU_GEM_DOMAIN_CPU,
|
||||
0, ttm_bo_type_sg, resv, &gobj);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
bo = gem_to_amdgpu_bo(gobj);
|
||||
bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
|
||||
bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
|
||||
if (dma_buf->ops != &amdgpu_dmabuf_ops)
|
||||
bo->prime_shared_count = 1;
|
||||
|
||||
dma_resv_unlock(resv);
|
||||
return &bo->tbo.base;
|
||||
return gobj;
|
||||
|
||||
error:
|
||||
dma_resv_unlock(resv);
|
||||
|
|
|
|||
|
|
@ -66,26 +66,12 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
|
|||
bp.type = type;
|
||||
bp.resv = resv;
|
||||
bp.preferred_domain = initial_domain;
|
||||
retry:
|
||||
bp.flags = flags;
|
||||
bp.domain = initial_domain;
|
||||
r = amdgpu_bo_create(adev, &bp, &bo);
|
||||
if (r) {
|
||||
if (r != -ERESTARTSYS) {
|
||||
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
|
||||
flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
|
||||
goto retry;
|
||||
}
|
||||
|
||||
if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
|
||||
initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
|
||||
goto retry;
|
||||
}
|
||||
DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
|
||||
size, initial_domain, alignment, r);
|
||||
}
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
*obj = &bo->tbo.base;
|
||||
|
||||
return 0;
|
||||
|
|
@ -225,7 +211,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
|
|||
uint64_t size = args->in.bo_size;
|
||||
struct dma_resv *resv = NULL;
|
||||
struct drm_gem_object *gobj;
|
||||
uint32_t handle;
|
||||
uint32_t handle, initial_domain;
|
||||
int r;
|
||||
|
||||
/* reject invalid gem flags */
|
||||
|
|
@ -269,9 +255,28 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
|
|||
resv = vm->root.base.bo->tbo.base.resv;
|
||||
}
|
||||
|
||||
retry:
|
||||
initial_domain = (u32)(0xffffffff & args->in.domains);
|
||||
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
|
||||
(u32)(0xffffffff & args->in.domains),
|
||||
initial_domain,
|
||||
flags, ttm_bo_type_device, resv, &gobj);
|
||||
if (r) {
|
||||
if (r != -ERESTARTSYS) {
|
||||
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
|
||||
flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
|
||||
goto retry;
|
||||
}
|
||||
|
||||
if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
|
||||
initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
|
||||
goto retry;
|
||||
}
|
||||
DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
|
||||
size, initial_domain, args->in.alignment, r);
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
|
||||
if (!r) {
|
||||
struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
|
||||
|
|
|
|||
|
|
@ -499,6 +499,9 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)
|
|||
else
|
||||
size = amdgpu_gmc_get_vbios_fb_size(adev);
|
||||
|
||||
if (adev->mman.keep_stolen_vga_memory)
|
||||
size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION);
|
||||
|
||||
/* set to 0 if the pre-OS buffer uses up most of vram */
|
||||
if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
|
||||
size = 0;
|
||||
|
|
|
|||
|
|
@ -1172,7 +1172,7 @@ static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
|
|||
con->dir, &con->disable_ras_err_cnt_harvest);
|
||||
}
|
||||
|
||||
void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
|
||||
static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
|
||||
struct ras_fs_if *head)
|
||||
{
|
||||
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
||||
|
|
@ -1194,7 +1194,6 @@ void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
|
|||
|
||||
void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
|
||||
{
|
||||
#if defined(CONFIG_DEBUG_FS)
|
||||
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
||||
struct ras_manager *obj;
|
||||
struct ras_fs_if fs_info;
|
||||
|
|
@ -1203,7 +1202,7 @@ void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
|
|||
* it won't be called in resume path, no need to check
|
||||
* suspend and gpu reset status
|
||||
*/
|
||||
if (!con)
|
||||
if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
|
||||
return;
|
||||
|
||||
amdgpu_ras_debugfs_create_ctrl_node(adev);
|
||||
|
|
@ -1217,10 +1216,9 @@ void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
|
|||
amdgpu_ras_debugfs_create(adev, &fs_info);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
|
||||
static void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
|
||||
struct ras_common_if *head)
|
||||
{
|
||||
struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
|
||||
|
|
@ -1234,7 +1232,6 @@ void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
|
|||
|
||||
static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
|
||||
{
|
||||
#if defined(CONFIG_DEBUG_FS)
|
||||
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
||||
struct ras_manager *obj, *tmp;
|
||||
|
||||
|
|
@ -1243,7 +1240,6 @@ static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
|
|||
}
|
||||
|
||||
con->dir = NULL;
|
||||
#endif
|
||||
}
|
||||
/* debugfs end */
|
||||
|
||||
|
|
@ -1291,7 +1287,8 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
|
|||
|
||||
static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
|
||||
{
|
||||
amdgpu_ras_debugfs_remove_all(adev);
|
||||
if (IS_ENABLED(CONFIG_DEBUG_FS))
|
||||
amdgpu_ras_debugfs_remove_all(adev);
|
||||
amdgpu_ras_sysfs_remove_all(adev);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -607,14 +607,8 @@ int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
|
|||
int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
|
||||
struct ras_common_if *head);
|
||||
|
||||
void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
|
||||
struct ras_fs_if *head);
|
||||
|
||||
void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
|
||||
|
||||
void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
|
||||
struct ras_common_if *head);
|
||||
|
||||
int amdgpu_ras_error_query(struct amdgpu_device *adev,
|
||||
struct ras_query_if *info);
|
||||
|
||||
|
|
|
|||
|
|
@ -186,7 +186,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
|
|||
if (err)
|
||||
goto out;
|
||||
|
||||
err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
|
||||
err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[i]);
|
||||
if (err)
|
||||
goto out;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1011,6 +1011,11 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
|
|||
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
|
||||
|
||||
/* Stall DPG before WPTR/RPTR reset */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
|
||||
UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
|
||||
~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
|
||||
|
||||
/* set the write pointer delay */
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
|
||||
|
||||
|
|
@ -1033,6 +1038,10 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
|
|||
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
|
||||
lower_32_bits(ring->wptr));
|
||||
|
||||
/* Unstall DPG */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
|
||||
0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1556,8 +1565,14 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
|
|||
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
|
||||
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
|
||||
|
||||
/* Stall DPG before WPTR/RPTR reset */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
|
||||
UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
|
||||
~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
|
||||
|
||||
/* Restore */
|
||||
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
|
||||
ring->wptr = 0;
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
|
||||
|
|
@ -1565,14 +1580,16 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
|
|||
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
|
||||
|
||||
ring = &adev->vcn.inst[inst_idx].ring_enc[1];
|
||||
ring->wptr = 0;
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
|
||||
|
||||
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
|
||||
RREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);
|
||||
/* Unstall DPG */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
|
||||
0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
|
||||
|
||||
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
|
||||
UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
|
|
@ -1630,10 +1647,6 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
|
|||
{
|
||||
struct amdgpu_device *adev = ring->adev;
|
||||
|
||||
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
|
||||
WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,
|
||||
lower_32_bits(ring->wptr) | 0x80000000);
|
||||
|
||||
if (ring->use_doorbell) {
|
||||
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
|
||||
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
|
||||
|
|
|
|||
|
|
@ -1736,6 +1736,7 @@ static int kfd_ioctl_import_dmabuf(struct file *filep,
|
|||
}
|
||||
|
||||
mutex_unlock(&p->mutex);
|
||||
dma_buf_put(dmabuf);
|
||||
|
||||
args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
|
||||
|
||||
|
|
@ -1745,6 +1746,7 @@ err_free:
|
|||
amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL);
|
||||
err_unlock:
|
||||
mutex_unlock(&p->mutex);
|
||||
dma_buf_put(dmabuf);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1058,9 +1058,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
|
|||
goto error;
|
||||
}
|
||||
|
||||
/* Update the actual used number of crtc */
|
||||
adev->mode_info.num_crtc = adev->dm.display_indexes_num;
|
||||
|
||||
/* create fake encoders for MST */
|
||||
dm_dp_create_fake_mst_encoders(adev);
|
||||
|
||||
|
|
@ -3251,6 +3248,10 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
|
|||
enum dc_connection_type new_connection_type = dc_connection_none;
|
||||
const struct dc_plane_cap *plane;
|
||||
|
||||
dm->display_indexes_num = dm->dc->caps.max_streams;
|
||||
/* Update the actual used number of crtc */
|
||||
adev->mode_info.num_crtc = adev->dm.display_indexes_num;
|
||||
|
||||
link_cnt = dm->dc->caps.max_links;
|
||||
if (amdgpu_dm_mode_config_init(dm->adev)) {
|
||||
DRM_ERROR("DM: Failed to initialize mode config\n");
|
||||
|
|
@ -3312,8 +3313,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
|
|||
goto fail;
|
||||
}
|
||||
|
||||
dm->display_indexes_num = dm->dc->caps.max_streams;
|
||||
|
||||
/* loops over all connectors on the board */
|
||||
for (i = 0; i < link_cnt; i++) {
|
||||
struct dc_link *link = NULL;
|
||||
|
|
|
|||
|
|
@ -163,8 +163,17 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
|
|||
new_clocks->dppclk_khz = 100000;
|
||||
}
|
||||
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
|
||||
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
|
||||
/*
|
||||
* Temporally ignore thew 0 cases for disp and dpp clks.
|
||||
* We may have a new feature that requires 0 clks in the future.
|
||||
*/
|
||||
if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) {
|
||||
new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz;
|
||||
new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz;
|
||||
}
|
||||
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
|
||||
if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
|
||||
dpp_clock_lowered = true;
|
||||
clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
|
||||
update_dppclk = true;
|
||||
|
|
@ -570,7 +579,7 @@ static struct clk_bw_params rn_bw_params = {
|
|||
|
||||
};
|
||||
|
||||
static struct wm_table ddr4_wm_table = {
|
||||
static struct wm_table ddr4_wm_table_gs = {
|
||||
.entries = {
|
||||
{
|
||||
.wm_inst = WM_A,
|
||||
|
|
@ -607,7 +616,7 @@ static struct wm_table ddr4_wm_table = {
|
|||
}
|
||||
};
|
||||
|
||||
static struct wm_table lpddr4_wm_table = {
|
||||
static struct wm_table lpddr4_wm_table_gs = {
|
||||
.entries = {
|
||||
{
|
||||
.wm_inst = WM_A,
|
||||
|
|
@ -681,6 +690,80 @@ static struct wm_table lpddr4_wm_table_with_disabled_ppt = {
|
|||
}
|
||||
};
|
||||
|
||||
static struct wm_table ddr4_wm_table_rn = {
|
||||
.entries = {
|
||||
{
|
||||
.wm_inst = WM_A,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.72,
|
||||
.sr_exit_time_us = 9.09,
|
||||
.sr_enter_plus_exit_time_us = 10.14,
|
||||
.valid = true,
|
||||
},
|
||||
{
|
||||
.wm_inst = WM_B,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.72,
|
||||
.sr_exit_time_us = 10.12,
|
||||
.sr_enter_plus_exit_time_us = 11.48,
|
||||
.valid = true,
|
||||
},
|
||||
{
|
||||
.wm_inst = WM_C,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.72,
|
||||
.sr_exit_time_us = 10.12,
|
||||
.sr_enter_plus_exit_time_us = 11.48,
|
||||
.valid = true,
|
||||
},
|
||||
{
|
||||
.wm_inst = WM_D,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.72,
|
||||
.sr_exit_time_us = 10.12,
|
||||
.sr_enter_plus_exit_time_us = 11.48,
|
||||
.valid = true,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
static struct wm_table lpddr4_wm_table_rn = {
|
||||
.entries = {
|
||||
{
|
||||
.wm_inst = WM_A,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.65333,
|
||||
.sr_exit_time_us = 7.32,
|
||||
.sr_enter_plus_exit_time_us = 8.38,
|
||||
.valid = true,
|
||||
},
|
||||
{
|
||||
.wm_inst = WM_B,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.65333,
|
||||
.sr_exit_time_us = 9.82,
|
||||
.sr_enter_plus_exit_time_us = 11.196,
|
||||
.valid = true,
|
||||
},
|
||||
{
|
||||
.wm_inst = WM_C,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.65333,
|
||||
.sr_exit_time_us = 9.89,
|
||||
.sr_enter_plus_exit_time_us = 11.24,
|
||||
.valid = true,
|
||||
},
|
||||
{
|
||||
.wm_inst = WM_D,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.65333,
|
||||
.sr_exit_time_us = 9.748,
|
||||
.sr_enter_plus_exit_time_us = 11.102,
|
||||
.valid = true,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -762,6 +845,11 @@ void rn_clk_mgr_construct(
|
|||
struct dc_debug_options *debug = &ctx->dc->debug;
|
||||
struct dpm_clocks clock_table = { 0 };
|
||||
enum pp_smu_status status = 0;
|
||||
int is_green_sardine = 0;
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN)
|
||||
is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev);
|
||||
#endif
|
||||
|
||||
clk_mgr->base.ctx = ctx;
|
||||
clk_mgr->base.funcs = &dcn21_funcs;
|
||||
|
|
@ -802,10 +890,16 @@ void rn_clk_mgr_construct(
|
|||
if (clk_mgr->periodic_retraining_disabled) {
|
||||
rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;
|
||||
} else {
|
||||
rn_bw_params.wm_table = lpddr4_wm_table;
|
||||
if (is_green_sardine)
|
||||
rn_bw_params.wm_table = lpddr4_wm_table_gs;
|
||||
else
|
||||
rn_bw_params.wm_table = lpddr4_wm_table_rn;
|
||||
}
|
||||
} else {
|
||||
rn_bw_params.wm_table = ddr4_wm_table;
|
||||
if (is_green_sardine)
|
||||
rn_bw_params.wm_table = ddr4_wm_table_gs;
|
||||
else
|
||||
rn_bw_params.wm_table = ddr4_wm_table_rn;
|
||||
}
|
||||
/* Saved clocks configured at boot for debug purposes */
|
||||
rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
|
||||
|
|
|
|||
|
|
@ -3394,10 +3394,13 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
|
|||
{
|
||||
uint32_t bits_per_channel = 0;
|
||||
uint32_t kbps;
|
||||
struct fixed31_32 link_bw_kbps;
|
||||
|
||||
if (timing->flags.DSC) {
|
||||
kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
|
||||
kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
|
||||
link_bw_kbps = dc_fixpt_from_int(timing->pix_clk_100hz);
|
||||
link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160);
|
||||
link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, timing->dsc_cfg.bits_per_pixel);
|
||||
kbps = dc_fixpt_ceil(link_bw_kbps);
|
||||
return kbps;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -136,14 +136,12 @@
|
|||
#define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT)
|
||||
|
||||
/* Workload bits */
|
||||
#define WORKLOAD_DEFAULT_BIT 0
|
||||
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
|
||||
#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
|
||||
#define WORKLOAD_PPLIB_VIDEO_BIT 3
|
||||
#define WORKLOAD_PPLIB_VR_BIT 4
|
||||
#define WORKLOAD_PPLIB_COMPUTE_BIT 5
|
||||
#define WORKLOAD_PPLIB_CUSTOM_BIT 6
|
||||
#define WORKLOAD_PPLIB_COUNT 7
|
||||
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
|
||||
#define WORKLOAD_PPLIB_VIDEO_BIT 2
|
||||
#define WORKLOAD_PPLIB_VR_BIT 3
|
||||
#define WORKLOAD_PPLIB_COMPUTE_BIT 4
|
||||
#define WORKLOAD_PPLIB_CUSTOM_BIT 5
|
||||
#define WORKLOAD_PPLIB_COUNT 6
|
||||
|
||||
typedef struct {
|
||||
/* MP1_EXT_SCRATCH0 */
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <drm/amdgpu_drm.h>
|
||||
#include "processpptables.h"
|
||||
#include <atom-types.h>
|
||||
|
|
@ -984,6 +986,8 @@ static int init_thermal_controller(
|
|||
struct pp_hwmgr *hwmgr,
|
||||
const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
|
||||
hwmgr->thermal_controller.ucType =
|
||||
powerplay_table->sThermalController.ucType;
|
||||
hwmgr->thermal_controller.ucI2cLine =
|
||||
|
|
@ -1008,7 +1012,104 @@ static int init_thermal_controller(
|
|||
ATOM_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
|
||||
PHM_PlatformCaps_ThermalController);
|
||||
|
||||
hwmgr->thermal_controller.use_hw_fan_control = 1;
|
||||
if (powerplay_table->usTableSize >= sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
|
||||
const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
|
||||
(const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
|
||||
|
||||
if (0 == le16_to_cpu(powerplay_table3->usFanTableOffset)) {
|
||||
hwmgr->thermal_controller.use_hw_fan_control = 1;
|
||||
return 0;
|
||||
} else {
|
||||
const ATOM_PPLIB_FANTABLE *fan_table =
|
||||
(const ATOM_PPLIB_FANTABLE *)(((unsigned long)powerplay_table) +
|
||||
le16_to_cpu(powerplay_table3->usFanTableOffset));
|
||||
|
||||
if (1 <= fan_table->ucFanTableFormat) {
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst =
|
||||
fan_table->ucTHyst;
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usTMin =
|
||||
le16_to_cpu(fan_table->usTMin);
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usTMed =
|
||||
le16_to_cpu(fan_table->usTMed);
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usTHigh =
|
||||
le16_to_cpu(fan_table->usTHigh);
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
|
||||
le16_to_cpu(fan_table->usPWMMin);
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed =
|
||||
le16_to_cpu(fan_table->usPWMMed);
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh =
|
||||
le16_to_cpu(fan_table->usPWMHigh);
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usTMax = 10900;
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay = 100000;
|
||||
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_MicrocodeFanControl);
|
||||
}
|
||||
|
||||
if (2 <= fan_table->ucFanTableFormat) {
|
||||
const ATOM_PPLIB_FANTABLE2 *fan_table2 =
|
||||
(const ATOM_PPLIB_FANTABLE2 *)(((unsigned long)powerplay_table) +
|
||||
le16_to_cpu(powerplay_table3->usFanTableOffset));
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
|
||||
le16_to_cpu(fan_table2->usTMax);
|
||||
}
|
||||
|
||||
if (3 <= fan_table->ucFanTableFormat) {
|
||||
const ATOM_PPLIB_FANTABLE3 *fan_table3 =
|
||||
(const ATOM_PPLIB_FANTABLE3 *) (((unsigned long)powerplay_table) +
|
||||
le16_to_cpu(powerplay_table3->usFanTableOffset));
|
||||
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode =
|
||||
fan_table3->ucFanControlMode;
|
||||
|
||||
if ((3 == fan_table->ucFanTableFormat) &&
|
||||
(0x67B1 == adev->pdev->device))
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM =
|
||||
47;
|
||||
else
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM =
|
||||
le16_to_cpu(fan_table3->usFanPWMMax);
|
||||
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity =
|
||||
4836;
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
|
||||
le16_to_cpu(fan_table3->usFanOutputSensitivity);
|
||||
}
|
||||
|
||||
if (6 <= fan_table->ucFanTableFormat) {
|
||||
const ATOM_PPLIB_FANTABLE4 *fan_table4 =
|
||||
(const ATOM_PPLIB_FANTABLE4 *)(((unsigned long)powerplay_table) +
|
||||
le16_to_cpu(powerplay_table3->usFanTableOffset));
|
||||
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_FanSpeedInTableIsRPM);
|
||||
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM =
|
||||
le16_to_cpu(fan_table4->usFanRPMMax);
|
||||
}
|
||||
|
||||
if (7 <= fan_table->ucFanTableFormat) {
|
||||
const ATOM_PPLIB_FANTABLE5 *fan_table5 =
|
||||
(const ATOM_PPLIB_FANTABLE5 *)(((unsigned long)powerplay_table) +
|
||||
le16_to_cpu(powerplay_table3->usFanTableOffset));
|
||||
|
||||
if (0x67A2 == adev->pdev->device ||
|
||||
0x67A9 == adev->pdev->device ||
|
||||
0x67B9 == adev->pdev->device) {
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_GeminiRegulatorFanControlSupport);
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usFanCurrentLow =
|
||||
le16_to_cpu(fan_table5->usFanCurrentLow);
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usFanCurrentHigh =
|
||||
le16_to_cpu(fan_table5->usFanCurrentHigh);
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMLow =
|
||||
le16_to_cpu(fan_table5->usFanRPMLow);
|
||||
hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMHigh =
|
||||
le16_to_cpu(fan_table5->usFanRPMHigh);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1297,15 +1297,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)
|
|||
int pplib_workload = 0;
|
||||
|
||||
switch (power_profile) {
|
||||
case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
|
||||
pplib_workload = WORKLOAD_DEFAULT_BIT;
|
||||
break;
|
||||
case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
|
||||
pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
|
||||
break;
|
||||
case PP_SMC_POWER_PROFILE_POWERSAVING:
|
||||
pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
|
||||
break;
|
||||
case PP_SMC_POWER_PROFILE_VIDEO:
|
||||
pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
|
||||
break;
|
||||
|
|
@ -1315,6 +1309,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)
|
|||
case PP_SMC_POWER_PROFILE_COMPUTE:
|
||||
pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
|
||||
break;
|
||||
case PP_SMC_POWER_PROFILE_CUSTOM:
|
||||
pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
|
||||
break;
|
||||
}
|
||||
|
||||
return pplib_workload;
|
||||
|
|
|
|||
|
|
@ -217,7 +217,7 @@ static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_
|
|||
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
|
||||
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
|
||||
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
|
||||
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
|
||||
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
|
||||
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1164,7 +1164,12 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
crystal_clock_freq = amdgpu_asic_get_xclk(adev);
|
||||
/*
|
||||
* crystal_clock_freq div by 4 is required since the fan control
|
||||
* module refers to 25MHz
|
||||
*/
|
||||
|
||||
crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
|
||||
tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
|
||||
WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
|
||||
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
|
||||
|
|
|
|||
|
|
@ -18021,16 +18021,6 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
|
|||
if (!HAS_GMCH(i915))
|
||||
sanitize_watermarks(i915);
|
||||
|
||||
/*
|
||||
* Force all active planes to recompute their states. So that on
|
||||
* mode_setcrtc after probe, all the intel_plane_state variables
|
||||
* are already calculated and there is no assert_plane warnings
|
||||
* during bootup.
|
||||
*/
|
||||
ret = intel_initial_commit(dev);
|
||||
if (ret)
|
||||
drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -18039,11 +18029,21 @@ int intel_modeset_init(struct drm_i915_private *i915)
|
|||
{
|
||||
int ret;
|
||||
|
||||
intel_overlay_setup(i915);
|
||||
|
||||
if (!HAS_DISPLAY(i915))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Force all active planes to recompute their states. So that on
|
||||
* mode_setcrtc after probe, all the intel_plane_state variables
|
||||
* are already calculated and there is no assert_plane warnings
|
||||
* during bootup.
|
||||
*/
|
||||
ret = intel_initial_commit(&i915->drm);
|
||||
if (ret)
|
||||
drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
|
||||
|
||||
intel_overlay_setup(i915);
|
||||
|
||||
ret = intel_fbdev_init(&i915->drm);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -573,7 +573,7 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
|
|||
return 0;
|
||||
}
|
||||
/* Also take into account max slice width */
|
||||
min_slice_count = min_t(u8, min_slice_count,
|
||||
min_slice_count = max_t(u8, min_slice_count,
|
||||
DIV_ROUND_UP(mode_hdisplay,
|
||||
max_slice_width));
|
||||
|
||||
|
|
|
|||
|
|
@ -3097,7 +3097,7 @@ static void retire_requests(struct intel_timeline *tl, struct i915_request *end)
|
|||
break;
|
||||
}
|
||||
|
||||
static void eb_request_add(struct i915_execbuffer *eb)
|
||||
static int eb_request_add(struct i915_execbuffer *eb, int err)
|
||||
{
|
||||
struct i915_request *rq = eb->request;
|
||||
struct intel_timeline * const tl = i915_request_timeline(rq);
|
||||
|
|
@ -3118,6 +3118,7 @@ static void eb_request_add(struct i915_execbuffer *eb)
|
|||
/* Serialise with context_close via the add_to_timeline */
|
||||
i915_request_set_error_once(rq, -ENOENT);
|
||||
__i915_request_skip(rq);
|
||||
err = -ENOENT; /* override any transient errors */
|
||||
}
|
||||
|
||||
__i915_request_queue(rq, &attr);
|
||||
|
|
@ -3127,6 +3128,8 @@ static void eb_request_add(struct i915_execbuffer *eb)
|
|||
retire_requests(tl, prev);
|
||||
|
||||
mutex_unlock(&tl->mutex);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static const i915_user_extension_fn execbuf_extensions[] = {
|
||||
|
|
@ -3332,7 +3335,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
|
|||
err = eb_submit(&eb, batch);
|
||||
err_request:
|
||||
i915_request_get(eb.request);
|
||||
eb_request_add(&eb);
|
||||
err = eb_request_add(&eb, err);
|
||||
|
||||
if (eb.fences)
|
||||
signal_fence_array(&eb);
|
||||
|
|
|
|||
|
|
@ -101,18 +101,37 @@ static void __intel_breadcrumbs_disarm_irq(struct intel_breadcrumbs *b)
|
|||
intel_gt_pm_put_async(b->irq_engine->gt);
|
||||
}
|
||||
|
||||
static void intel_breadcrumbs_disarm_irq(struct intel_breadcrumbs *b)
|
||||
{
|
||||
spin_lock(&b->irq_lock);
|
||||
if (b->irq_armed)
|
||||
__intel_breadcrumbs_disarm_irq(b);
|
||||
spin_unlock(&b->irq_lock);
|
||||
}
|
||||
|
||||
static void add_signaling_context(struct intel_breadcrumbs *b,
|
||||
struct intel_context *ce)
|
||||
{
|
||||
intel_context_get(ce);
|
||||
list_add_tail(&ce->signal_link, &b->signalers);
|
||||
lockdep_assert_held(&ce->signal_lock);
|
||||
|
||||
spin_lock(&b->signalers_lock);
|
||||
list_add_rcu(&ce->signal_link, &b->signalers);
|
||||
spin_unlock(&b->signalers_lock);
|
||||
}
|
||||
|
||||
static void remove_signaling_context(struct intel_breadcrumbs *b,
|
||||
static bool remove_signaling_context(struct intel_breadcrumbs *b,
|
||||
struct intel_context *ce)
|
||||
{
|
||||
list_del(&ce->signal_link);
|
||||
intel_context_put(ce);
|
||||
lockdep_assert_held(&ce->signal_lock);
|
||||
|
||||
if (!list_empty(&ce->signals))
|
||||
return false;
|
||||
|
||||
spin_lock(&b->signalers_lock);
|
||||
list_del_rcu(&ce->signal_link);
|
||||
spin_unlock(&b->signalers_lock);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool __request_completed(const struct i915_request *rq)
|
||||
|
|
@ -175,6 +194,8 @@ static void add_retire(struct intel_breadcrumbs *b, struct intel_timeline *tl)
|
|||
|
||||
static bool __signal_request(struct i915_request *rq)
|
||||
{
|
||||
GEM_BUG_ON(test_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags));
|
||||
|
||||
if (!__dma_fence_signal(&rq->fence)) {
|
||||
i915_request_put(rq);
|
||||
return false;
|
||||
|
|
@ -195,15 +216,12 @@ static void signal_irq_work(struct irq_work *work)
|
|||
struct intel_breadcrumbs *b = container_of(work, typeof(*b), irq_work);
|
||||
const ktime_t timestamp = ktime_get();
|
||||
struct llist_node *signal, *sn;
|
||||
struct intel_context *ce, *cn;
|
||||
struct list_head *pos, *next;
|
||||
struct intel_context *ce;
|
||||
|
||||
signal = NULL;
|
||||
if (unlikely(!llist_empty(&b->signaled_requests)))
|
||||
signal = llist_del_all(&b->signaled_requests);
|
||||
|
||||
spin_lock(&b->irq_lock);
|
||||
|
||||
/*
|
||||
* Keep the irq armed until the interrupt after all listeners are gone.
|
||||
*
|
||||
|
|
@ -229,47 +247,44 @@ static void signal_irq_work(struct irq_work *work)
|
|||
* interrupt draw less ire from other users of the system and tools
|
||||
* like powertop.
|
||||
*/
|
||||
if (!signal && b->irq_armed && list_empty(&b->signalers))
|
||||
__intel_breadcrumbs_disarm_irq(b);
|
||||
if (!signal && READ_ONCE(b->irq_armed) && list_empty(&b->signalers))
|
||||
intel_breadcrumbs_disarm_irq(b);
|
||||
|
||||
list_for_each_entry_safe(ce, cn, &b->signalers, signal_link) {
|
||||
GEM_BUG_ON(list_empty(&ce->signals));
|
||||
rcu_read_lock();
|
||||
list_for_each_entry_rcu(ce, &b->signalers, signal_link) {
|
||||
struct i915_request *rq;
|
||||
|
||||
list_for_each_safe(pos, next, &ce->signals) {
|
||||
struct i915_request *rq =
|
||||
list_entry(pos, typeof(*rq), signal_link);
|
||||
list_for_each_entry_rcu(rq, &ce->signals, signal_link) {
|
||||
bool release;
|
||||
|
||||
GEM_BUG_ON(!check_signal_order(ce, rq));
|
||||
if (!__request_completed(rq))
|
||||
break;
|
||||
|
||||
if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL,
|
||||
&rq->fence.flags))
|
||||
break;
|
||||
|
||||
/*
|
||||
* Queue for execution after dropping the signaling
|
||||
* spinlock as the callback chain may end up adding
|
||||
* more signalers to the same context or engine.
|
||||
*/
|
||||
clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags);
|
||||
spin_lock(&ce->signal_lock);
|
||||
list_del_rcu(&rq->signal_link);
|
||||
release = remove_signaling_context(b, ce);
|
||||
spin_unlock(&ce->signal_lock);
|
||||
|
||||
if (__signal_request(rq))
|
||||
/* We own signal_node now, xfer to local list */
|
||||
signal = slist_add(&rq->signal_node, signal);
|
||||
}
|
||||
|
||||
/*
|
||||
* We process the list deletion in bulk, only using a list_add
|
||||
* (not list_move) above but keeping the status of
|
||||
* rq->signal_link known with the I915_FENCE_FLAG_SIGNAL bit.
|
||||
*/
|
||||
if (!list_is_first(pos, &ce->signals)) {
|
||||
/* Advance the list to the first incomplete request */
|
||||
__list_del_many(&ce->signals, pos);
|
||||
if (&ce->signals == pos) { /* now empty */
|
||||
if (release) {
|
||||
add_retire(b, ce->timeline);
|
||||
remove_signaling_context(b, ce);
|
||||
intel_context_put(ce);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock(&b->irq_lock);
|
||||
rcu_read_unlock();
|
||||
|
||||
llist_for_each_safe(signal, sn, signal) {
|
||||
struct i915_request *rq =
|
||||
|
|
@ -298,14 +313,15 @@ intel_breadcrumbs_create(struct intel_engine_cs *irq_engine)
|
|||
if (!b)
|
||||
return NULL;
|
||||
|
||||
spin_lock_init(&b->irq_lock);
|
||||
b->irq_engine = irq_engine;
|
||||
|
||||
spin_lock_init(&b->signalers_lock);
|
||||
INIT_LIST_HEAD(&b->signalers);
|
||||
init_llist_head(&b->signaled_requests);
|
||||
|
||||
spin_lock_init(&b->irq_lock);
|
||||
init_irq_work(&b->irq_work, signal_irq_work);
|
||||
|
||||
b->irq_engine = irq_engine;
|
||||
|
||||
return b;
|
||||
}
|
||||
|
||||
|
|
@ -347,9 +363,9 @@ void intel_breadcrumbs_free(struct intel_breadcrumbs *b)
|
|||
kfree(b);
|
||||
}
|
||||
|
||||
static void insert_breadcrumb(struct i915_request *rq,
|
||||
struct intel_breadcrumbs *b)
|
||||
static void insert_breadcrumb(struct i915_request *rq)
|
||||
{
|
||||
struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs;
|
||||
struct intel_context *ce = rq->context;
|
||||
struct list_head *pos;
|
||||
|
||||
|
|
@ -371,6 +387,7 @@ static void insert_breadcrumb(struct i915_request *rq,
|
|||
}
|
||||
|
||||
if (list_empty(&ce->signals)) {
|
||||
intel_context_get(ce);
|
||||
add_signaling_context(b, ce);
|
||||
pos = &ce->signals;
|
||||
} else {
|
||||
|
|
@ -396,8 +413,9 @@ static void insert_breadcrumb(struct i915_request *rq,
|
|||
break;
|
||||
}
|
||||
}
|
||||
list_add(&rq->signal_link, pos);
|
||||
list_add_rcu(&rq->signal_link, pos);
|
||||
GEM_BUG_ON(!check_signal_order(ce, rq));
|
||||
GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags));
|
||||
set_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags);
|
||||
|
||||
/*
|
||||
|
|
@ -410,7 +428,7 @@ static void insert_breadcrumb(struct i915_request *rq,
|
|||
|
||||
bool i915_request_enable_breadcrumb(struct i915_request *rq)
|
||||
{
|
||||
struct intel_breadcrumbs *b;
|
||||
struct intel_context *ce = rq->context;
|
||||
|
||||
/* Serialises with i915_request_retire() using rq->lock */
|
||||
if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
|
||||
|
|
@ -425,67 +443,30 @@ bool i915_request_enable_breadcrumb(struct i915_request *rq)
|
|||
if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags))
|
||||
return true;
|
||||
|
||||
/*
|
||||
* rq->engine is locked by rq->engine->active.lock. That however
|
||||
* is not known until after rq->engine has been dereferenced and
|
||||
* the lock acquired. Hence we acquire the lock and then validate
|
||||
* that rq->engine still matches the lock we hold for it.
|
||||
*
|
||||
* Here, we are using the breadcrumb lock as a proxy for the
|
||||
* rq->engine->active.lock, and we know that since the breadcrumb
|
||||
* will be serialised within i915_request_submit/i915_request_unsubmit,
|
||||
* the engine cannot change while active as long as we hold the
|
||||
* breadcrumb lock on that engine.
|
||||
*
|
||||
* From the dma_fence_enable_signaling() path, we are outside of the
|
||||
* request submit/unsubmit path, and so we must be more careful to
|
||||
* acquire the right lock.
|
||||
*/
|
||||
b = READ_ONCE(rq->engine)->breadcrumbs;
|
||||
spin_lock(&b->irq_lock);
|
||||
while (unlikely(b != READ_ONCE(rq->engine)->breadcrumbs)) {
|
||||
spin_unlock(&b->irq_lock);
|
||||
b = READ_ONCE(rq->engine)->breadcrumbs;
|
||||
spin_lock(&b->irq_lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* Now that we are finally serialised with request submit/unsubmit,
|
||||
* [with b->irq_lock] and with i915_request_retire() [via checking
|
||||
* SIGNALED with rq->lock] confirm the request is indeed active. If
|
||||
* it is no longer active, the breadcrumb will be attached upon
|
||||
* i915_request_submit().
|
||||
*/
|
||||
spin_lock(&ce->signal_lock);
|
||||
if (test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags))
|
||||
insert_breadcrumb(rq, b);
|
||||
|
||||
spin_unlock(&b->irq_lock);
|
||||
insert_breadcrumb(rq);
|
||||
spin_unlock(&ce->signal_lock);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void i915_request_cancel_breadcrumb(struct i915_request *rq)
|
||||
{
|
||||
struct intel_breadcrumbs *b = rq->engine->breadcrumbs;
|
||||
struct intel_context *ce = rq->context;
|
||||
bool release;
|
||||
|
||||
/*
|
||||
* We must wait for b->irq_lock so that we know the interrupt handler
|
||||
* has released its reference to the intel_context and has completed
|
||||
* the DMA_FENCE_FLAG_SIGNALED_BIT/I915_FENCE_FLAG_SIGNAL dance (if
|
||||
* required).
|
||||
*/
|
||||
spin_lock(&b->irq_lock);
|
||||
if (test_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags)) {
|
||||
struct intel_context *ce = rq->context;
|
||||
if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags))
|
||||
return;
|
||||
|
||||
list_del(&rq->signal_link);
|
||||
if (list_empty(&ce->signals))
|
||||
remove_signaling_context(b, ce);
|
||||
spin_lock(&ce->signal_lock);
|
||||
list_del_rcu(&rq->signal_link);
|
||||
release = remove_signaling_context(rq->engine->breadcrumbs, ce);
|
||||
spin_unlock(&ce->signal_lock);
|
||||
if (release)
|
||||
intel_context_put(ce);
|
||||
|
||||
clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags);
|
||||
i915_request_put(rq);
|
||||
}
|
||||
spin_unlock(&b->irq_lock);
|
||||
i915_request_put(rq);
|
||||
}
|
||||
|
||||
static void print_signals(struct intel_breadcrumbs *b, struct drm_printer *p)
|
||||
|
|
@ -495,18 +476,17 @@ static void print_signals(struct intel_breadcrumbs *b, struct drm_printer *p)
|
|||
|
||||
drm_printf(p, "Signals:\n");
|
||||
|
||||
spin_lock_irq(&b->irq_lock);
|
||||
list_for_each_entry(ce, &b->signalers, signal_link) {
|
||||
list_for_each_entry(rq, &ce->signals, signal_link) {
|
||||
rcu_read_lock();
|
||||
list_for_each_entry_rcu(ce, &b->signalers, signal_link) {
|
||||
list_for_each_entry_rcu(rq, &ce->signals, signal_link)
|
||||
drm_printf(p, "\t[%llx:%llx%s] @ %dms\n",
|
||||
rq->fence.context, rq->fence.seqno,
|
||||
i915_request_completed(rq) ? "!" :
|
||||
i915_request_started(rq) ? "*" :
|
||||
"",
|
||||
jiffies_to_msecs(jiffies - rq->emitted_jiffies));
|
||||
}
|
||||
}
|
||||
spin_unlock_irq(&b->irq_lock);
|
||||
rcu_read_unlock();
|
||||
}
|
||||
|
||||
void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
|
||||
|
|
|
|||
|
|
@ -29,18 +29,16 @@
|
|||
* the overhead of waking that client is much preferred.
|
||||
*/
|
||||
struct intel_breadcrumbs {
|
||||
spinlock_t irq_lock; /* protects the lists used in hardirq context */
|
||||
|
||||
/* Not all breadcrumbs are attached to physical HW */
|
||||
struct intel_engine_cs *irq_engine;
|
||||
|
||||
spinlock_t signalers_lock; /* protects the list of signalers */
|
||||
struct list_head signalers;
|
||||
struct llist_head signaled_requests;
|
||||
|
||||
spinlock_t irq_lock; /* protects the interrupt from hardirq context */
|
||||
struct irq_work irq_work; /* for use from inside irq_lock */
|
||||
|
||||
unsigned int irq_enabled;
|
||||
|
||||
bool irq_armed;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -25,9 +25,16 @@ static struct intel_context *intel_context_alloc(void)
|
|||
return kmem_cache_zalloc(global.slab_ce, GFP_KERNEL);
|
||||
}
|
||||
|
||||
static void rcu_context_free(struct rcu_head *rcu)
|
||||
{
|
||||
struct intel_context *ce = container_of(rcu, typeof(*ce), rcu);
|
||||
|
||||
kmem_cache_free(global.slab_ce, ce);
|
||||
}
|
||||
|
||||
void intel_context_free(struct intel_context *ce)
|
||||
{
|
||||
kmem_cache_free(global.slab_ce, ce);
|
||||
call_rcu(&ce->rcu, rcu_context_free);
|
||||
}
|
||||
|
||||
struct intel_context *
|
||||
|
|
@ -356,8 +363,7 @@ static int __intel_context_active(struct i915_active *active)
|
|||
}
|
||||
|
||||
void
|
||||
intel_context_init(struct intel_context *ce,
|
||||
struct intel_engine_cs *engine)
|
||||
intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)
|
||||
{
|
||||
GEM_BUG_ON(!engine->cops);
|
||||
GEM_BUG_ON(!engine->gt->vm);
|
||||
|
|
@ -373,7 +379,8 @@ intel_context_init(struct intel_context *ce,
|
|||
|
||||
ce->vm = i915_vm_get(engine->gt->vm);
|
||||
|
||||
INIT_LIST_HEAD(&ce->signal_link);
|
||||
/* NB ce->signal_link/lock is used under RCU */
|
||||
spin_lock_init(&ce->signal_lock);
|
||||
INIT_LIST_HEAD(&ce->signals);
|
||||
|
||||
mutex_init(&ce->pin_mutex);
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ DECLARE_EWMA(runtime, 3, 8);
|
|||
struct i915_gem_context;
|
||||
struct i915_gem_ww_ctx;
|
||||
struct i915_vma;
|
||||
struct intel_breadcrumbs;
|
||||
struct intel_context;
|
||||
struct intel_ring;
|
||||
|
||||
|
|
@ -44,7 +45,16 @@ struct intel_context_ops {
|
|||
};
|
||||
|
||||
struct intel_context {
|
||||
struct kref ref;
|
||||
/*
|
||||
* Note: Some fields may be accessed under RCU.
|
||||
*
|
||||
* Unless otherwise noted a field can safely be assumed to be protected
|
||||
* by strong reference counting.
|
||||
*/
|
||||
union {
|
||||
struct kref ref; /* no kref_get_unless_zero()! */
|
||||
struct rcu_head rcu;
|
||||
};
|
||||
|
||||
struct intel_engine_cs *engine;
|
||||
struct intel_engine_cs *inflight;
|
||||
|
|
@ -54,8 +64,15 @@ struct intel_context {
|
|||
struct i915_address_space *vm;
|
||||
struct i915_gem_context __rcu *gem_context;
|
||||
|
||||
struct list_head signal_link;
|
||||
struct list_head signals;
|
||||
/*
|
||||
* @signal_lock protects the list of requests that need signaling,
|
||||
* @signals. While there are any requests that need signaling,
|
||||
* we add the context to the breadcrumbs worker, and remove it
|
||||
* upon completion/cancellation of the last request.
|
||||
*/
|
||||
struct list_head signal_link; /* Accessed under RCU */
|
||||
struct list_head signals; /* Guarded by signal_lock */
|
||||
spinlock_t signal_lock; /* protects signals, the list of requests */
|
||||
|
||||
struct i915_vma *state;
|
||||
struct intel_ring *ring;
|
||||
|
|
|
|||
|
|
@ -2788,6 +2788,9 @@ static void __execlists_hold(struct i915_request *rq)
|
|||
static bool execlists_hold(struct intel_engine_cs *engine,
|
||||
struct i915_request *rq)
|
||||
{
|
||||
if (i915_request_on_hold(rq))
|
||||
return false;
|
||||
|
||||
spin_lock_irq(&engine->active.lock);
|
||||
|
||||
if (i915_request_completed(rq)) { /* too late! */
|
||||
|
|
@ -3169,8 +3172,10 @@ static void execlists_submission_tasklet(unsigned long data)
|
|||
spin_unlock_irqrestore(&engine->active.lock, flags);
|
||||
|
||||
/* Recheck after serialising with direct-submission */
|
||||
if (unlikely(timeout && preempt_timeout(engine)))
|
||||
if (unlikely(timeout && preempt_timeout(engine))) {
|
||||
cancel_timer(&engine->execlists.preempt);
|
||||
execlists_reset(engine, "preemption time out");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -59,8 +59,7 @@ struct drm_i915_mocs_table {
|
|||
#define _L3_CACHEABILITY(value) ((value) << 4)
|
||||
|
||||
/* Helper defines */
|
||||
#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
|
||||
#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
|
||||
#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
|
||||
|
||||
/* (e)LLC caching options */
|
||||
/*
|
||||
|
|
@ -131,7 +130,19 @@ static const struct drm_i915_mocs_entry skl_mocs_table[] = {
|
|||
GEN9_MOCS_ENTRIES,
|
||||
MOCS_ENTRY(I915_MOCS_CACHED,
|
||||
LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
|
||||
L3_3_WB)
|
||||
L3_3_WB),
|
||||
|
||||
/*
|
||||
* mocs:63
|
||||
* - used by the L3 for all of its evictions.
|
||||
* Thus it is expected to allow LLC cacheability to enable coherent
|
||||
* flows to be maintained.
|
||||
* - used to force L3 uncachable cycles.
|
||||
* Thus it is expected to make the surface L3 uncacheable.
|
||||
*/
|
||||
MOCS_ENTRY(63,
|
||||
LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
|
||||
L3_1_UC)
|
||||
};
|
||||
|
||||
/* NOTE: the LE_TGT_CACHE is not used on Broxton */
|
||||
|
|
@ -316,11 +327,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
|
|||
if (INTEL_GEN(i915) >= 12) {
|
||||
table->size = ARRAY_SIZE(tgl_mocs_table);
|
||||
table->table = tgl_mocs_table;
|
||||
table->n_entries = GEN11_NUM_MOCS_ENTRIES;
|
||||
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
|
||||
} else if (IS_GEN(i915, 11)) {
|
||||
table->size = ARRAY_SIZE(icl_mocs_table);
|
||||
table->table = icl_mocs_table;
|
||||
table->n_entries = GEN11_NUM_MOCS_ENTRIES;
|
||||
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
|
||||
} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
|
||||
table->size = ARRAY_SIZE(skl_mocs_table);
|
||||
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
|
||||
|
|
|
|||
|
|
@ -883,6 +883,10 @@ void intel_rps_park(struct intel_rps *rps)
|
|||
adj = -2;
|
||||
rps->last_adj = adj;
|
||||
rps->cur_freq = max_t(int, rps->cur_freq + adj, rps->min_freq);
|
||||
if (rps->cur_freq < rps->efficient_freq) {
|
||||
rps->cur_freq = rps->efficient_freq;
|
||||
rps->last_adj = 0;
|
||||
}
|
||||
|
||||
GT_TRACE(rps_to_gt(rps), "park:%x\n", rps->cur_freq);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ void *shmem_pin_map(struct file *file)
|
|||
mapping_set_unevictable(file->f_mapping);
|
||||
return vaddr;
|
||||
err_page:
|
||||
while (--i >= 0)
|
||||
while (i--)
|
||||
put_page(pages[i]);
|
||||
kvfree(pages);
|
||||
return NULL;
|
||||
|
|
@ -103,10 +103,13 @@ static int __shmem_rw(struct file *file, loff_t off,
|
|||
return PTR_ERR(page);
|
||||
|
||||
vaddr = kmap(page);
|
||||
if (write)
|
||||
if (write) {
|
||||
memcpy(vaddr + offset_in_page(off), ptr, this);
|
||||
else
|
||||
set_page_dirty(page);
|
||||
} else {
|
||||
memcpy(ptr, vaddr + offset_in_page(off), this);
|
||||
}
|
||||
mark_page_accessed(page);
|
||||
kunmap(page);
|
||||
put_page(page);
|
||||
|
||||
|
|
|
|||
|
|
@ -177,10 +177,8 @@ struct i915_request {
|
|||
struct intel_ring *ring;
|
||||
struct intel_timeline __rcu *timeline;
|
||||
|
||||
union {
|
||||
struct list_head signal_link;
|
||||
struct llist_node signal_node;
|
||||
};
|
||||
struct list_head signal_link;
|
||||
struct llist_node signal_node;
|
||||
|
||||
/*
|
||||
* The rcu epoch of when this request was allocated. Used to judiciously
|
||||
|
|
|
|||
|
|
@ -211,8 +211,8 @@ static int igt_gem_ww_ctx(void *arg)
|
|||
return PTR_ERR(obj);
|
||||
|
||||
obj2 = i915_gem_object_create_internal(i915, PAGE_SIZE);
|
||||
if (IS_ERR(obj)) {
|
||||
err = PTR_ERR(obj);
|
||||
if (IS_ERR(obj2)) {
|
||||
err = PTR_ERR(obj2);
|
||||
goto put1;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <drm/drm_fb_cma_helper.h>
|
||||
#include <drm/drm_fourcc.h>
|
||||
#include <drm/drm_gem_cma_helper.h>
|
||||
#include <drm/drm_gem_framebuffer_helper.h>
|
||||
#include <drm/drm_plane.h>
|
||||
#include <drm/drm_plane_helper.h>
|
||||
#include <drm/drm_vblank.h>
|
||||
|
|
@ -484,17 +485,27 @@ static void mxsfb_plane_overlay_atomic_update(struct drm_plane *plane,
|
|||
writel(ctrl, mxsfb->base + LCDC_AS_CTRL);
|
||||
}
|
||||
|
||||
static bool mxsfb_format_mod_supported(struct drm_plane *plane,
|
||||
uint32_t format,
|
||||
uint64_t modifier)
|
||||
{
|
||||
return modifier == DRM_FORMAT_MOD_LINEAR;
|
||||
}
|
||||
|
||||
static const struct drm_plane_helper_funcs mxsfb_plane_primary_helper_funcs = {
|
||||
.prepare_fb = drm_gem_fb_prepare_fb,
|
||||
.atomic_check = mxsfb_plane_atomic_check,
|
||||
.atomic_update = mxsfb_plane_primary_atomic_update,
|
||||
};
|
||||
|
||||
static const struct drm_plane_helper_funcs mxsfb_plane_overlay_helper_funcs = {
|
||||
.prepare_fb = drm_gem_fb_prepare_fb,
|
||||
.atomic_check = mxsfb_plane_atomic_check,
|
||||
.atomic_update = mxsfb_plane_overlay_atomic_update,
|
||||
};
|
||||
|
||||
static const struct drm_plane_funcs mxsfb_plane_funcs = {
|
||||
.format_mod_supported = mxsfb_format_mod_supported,
|
||||
.update_plane = drm_atomic_helper_update_plane,
|
||||
.disable_plane = drm_atomic_helper_disable_plane,
|
||||
.destroy = drm_plane_cleanup,
|
||||
|
|
|
|||
|
|
@ -1214,8 +1214,8 @@ retry:
|
|||
}
|
||||
|
||||
reg->bus.offset = handle;
|
||||
ret = 0;
|
||||
}
|
||||
ret = 0;
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
|
|
|
|||
|
|
@ -195,8 +195,7 @@ static void sdi_bridge_mode_set(struct drm_bridge *bridge,
|
|||
sdi->pixelclock = adjusted_mode->clock * 1000;
|
||||
}
|
||||
|
||||
static void sdi_bridge_enable(struct drm_bridge *bridge,
|
||||
struct drm_bridge_state *bridge_state)
|
||||
static void sdi_bridge_enable(struct drm_bridge *bridge)
|
||||
{
|
||||
struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
|
||||
struct dispc_clock_info dispc_cinfo;
|
||||
|
|
@ -259,8 +258,7 @@ err_get_dispc:
|
|||
regulator_disable(sdi->vdds_sdi_reg);
|
||||
}
|
||||
|
||||
static void sdi_bridge_disable(struct drm_bridge *bridge,
|
||||
struct drm_bridge_state *bridge_state)
|
||||
static void sdi_bridge_disable(struct drm_bridge *bridge)
|
||||
{
|
||||
struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
|
||||
|
||||
|
|
@ -278,8 +276,8 @@ static const struct drm_bridge_funcs sdi_bridge_funcs = {
|
|||
.mode_valid = sdi_bridge_mode_valid,
|
||||
.mode_fixup = sdi_bridge_mode_fixup,
|
||||
.mode_set = sdi_bridge_mode_set,
|
||||
.atomic_enable = sdi_bridge_enable,
|
||||
.atomic_disable = sdi_bridge_disable,
|
||||
.enable = sdi_bridge_enable,
|
||||
.disable = sdi_bridge_disable,
|
||||
};
|
||||
|
||||
static void sdi_bridge_init(struct sdi_device *sdi)
|
||||
|
|
|
|||
|
|
@ -629,7 +629,7 @@ static int acx565akm_probe(struct spi_device *spi)
|
|||
lcd->spi = spi;
|
||||
mutex_init(&lcd->mutex);
|
||||
|
||||
lcd->reset_gpio = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_LOW);
|
||||
lcd->reset_gpio = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(lcd->reset_gpio)) {
|
||||
dev_err(&spi->dev, "failed to get reset GPIO\n");
|
||||
return PTR_ERR(lcd->reset_gpio);
|
||||
|
|
|
|||
|
|
@ -544,7 +544,7 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master,
|
|||
struct device_node *port, *endpoint;
|
||||
int ret = 0, child_count = 0;
|
||||
const char *name;
|
||||
u32 endpoint_id;
|
||||
u32 endpoint_id = 0;
|
||||
|
||||
lvds->drm_dev = drm_dev;
|
||||
port = of_graph_get_port_by_id(dev->of_node, 1);
|
||||
|
|
|
|||
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