[SCSI] tmscsim: remove bogus endianness conversions
cpu_to_le32 endianness conversions in tmscsim.c, followed by arithmetic operations don't look correct. Besides, {in,out}[wl] already perform the necessary conversions. Further, bus addresses of request buffers are guaranteed to be (mapped) under 4G by current scsi- and block-layer defaults. This could be explicitly enforced by using blk_queue_bounce_limit(), which, however, doesn't seem to be the common practice among SCSI drivers. Signed-off-by: G. Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
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860bfecf71
Коммит
46e5ba2b64
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@ -778,8 +778,8 @@ dc390_DataOut_0( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
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pSRB->pSegmentList++;
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psgl = pSRB->pSegmentList;
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pSRB->SGBusAddr = cpu_to_le32(pci_dma_lo32(sg_dma_address(psgl)));
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pSRB->SGToBeXferLen = cpu_to_le32(sg_dma_len(psgl));
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pSRB->SGBusAddr = sg_dma_address(psgl);
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pSRB->SGToBeXferLen = sg_dma_len(psgl);
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}
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else
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pSRB->SGToBeXferLen = 0;
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@ -842,7 +842,7 @@ dc390_DataIn_0( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
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DEBUG1(ResidCnt = ((unsigned long) DC390_read8 (CtcReg_High) << 16) \
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+ ((unsigned long) DC390_read8 (CtcReg_Mid) << 8) \
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+ ((unsigned long) DC390_read8 (CtcReg_Low)));
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DEBUG1(printk (KERN_DEBUG "Count_2_Zero (ResidCnt=%i,ToBeXfer=%li),", ResidCnt, pSRB->SGToBeXferLen));
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DEBUG1(printk (KERN_DEBUG "Count_2_Zero (ResidCnt=%u,ToBeXfer=%lu),", ResidCnt, pSRB->SGToBeXferLen));
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DC390_write8 (DMA_Cmd, READ_DIRECTION+DMA_IDLE_CMD);
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@ -853,8 +853,8 @@ dc390_DataIn_0( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
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pSRB->pSegmentList++;
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psgl = pSRB->pSegmentList;
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pSRB->SGBusAddr = cpu_to_le32(pci_dma_lo32(sg_dma_address(psgl)));
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pSRB->SGToBeXferLen = cpu_to_le32(sg_dma_len(psgl));
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pSRB->SGBusAddr = sg_dma_address(psgl);
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pSRB->SGToBeXferLen = sg_dma_len(psgl);
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}
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else
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pSRB->SGToBeXferLen = 0;
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@ -921,11 +921,12 @@ din_1:
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ptr = (u8 *) bus_to_virt( pSRB->SGBusAddr );
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*ptr = bval;
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pSRB->SGBusAddr++; xferCnt++;
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pSRB->SGBusAddr++;
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xferCnt++;
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pSRB->TotalXferredLen++;
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pSRB->SGToBeXferLen--;
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}
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DEBUG1(printk (KERN_DEBUG "Xfered: %li, Total: %li, Remaining: %li\n", xferCnt,\
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DEBUG1(printk (KERN_DEBUG "Xfered: %lu, Total: %lu, Remaining: %lu\n", xferCnt,\
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pSRB->TotalXferredLen, pSRB->SGToBeXferLen));
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}
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@ -1157,14 +1158,14 @@ dc390_restore_ptr (struct dc390_acb* pACB, struct dc390_srb* pSRB)
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{
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pSRB->pSegmentList++;
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psgl = pSRB->pSegmentList;
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pSRB->SGBusAddr = cpu_to_le32(pci_dma_lo32(sg_dma_address(psgl)));
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pSRB->SGToBeXferLen = cpu_to_le32(sg_dma_len(psgl));
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pSRB->SGBusAddr = sg_dma_address(psgl);
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pSRB->SGToBeXferLen = sg_dma_len(psgl);
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}
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else
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pSRB->SGToBeXferLen = 0;
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}
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pSRB->SGToBeXferLen -= (pSRB->Saved_Ptr - pSRB->TotalXferredLen);
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pSRB->SGBusAddr += (pSRB->Saved_Ptr - pSRB->TotalXferredLen);
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pSRB->SGToBeXferLen -= pSRB->Saved_Ptr - pSRB->TotalXferredLen;
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pSRB->SGBusAddr += pSRB->Saved_Ptr - pSRB->TotalXferredLen;
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printk (KERN_INFO "DC390: Pointer restored. Segment %i, Total %li, Bus %08lx\n",
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pSRB->SGIndex, pSRB->Saved_Ptr, pSRB->SGBusAddr);
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@ -1315,8 +1316,8 @@ dc390_DataIO_Comm( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 ioDir)
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if( !pSRB->SGToBeXferLen )
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{
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psgl = pSRB->pSegmentList;
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pSRB->SGBusAddr = cpu_to_le32(pci_dma_lo32(sg_dma_address(psgl)));
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pSRB->SGToBeXferLen = cpu_to_le32(sg_dma_len(psgl));
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pSRB->SGBusAddr = sg_dma_address(psgl);
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pSRB->SGToBeXferLen = sg_dma_len(psgl);
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DEBUG1(printk (KERN_DEBUG " DC390: Next SG segment."));
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}
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lval = pSRB->SGToBeXferLen;
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@ -19,14 +19,6 @@
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#define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
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#define pci_dma_lo32(a) (a & 0xffffffff)
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typedef u8 UCHAR; /* 8 bits */
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typedef u16 USHORT; /* 16 bits */
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typedef u32 UINT; /* 32 bits */
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typedef unsigned long ULONG; /* 32/64 bits */
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/*
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;-----------------------------------------------------------------------
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; SCSI Request Block
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@ -43,7 +35,9 @@ struct scatterlist *pSegmentList;
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struct scatterlist Segmentx; /* make a one entry of S/G list table */
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unsigned long SGBusAddr; /*;a segment starting address as seen by AM53C974A*/
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unsigned long SGBusAddr; /*;a segment starting address as seen by AM53C974A
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in CPU endianness. We're only getting 32-bit bus
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addresses by default */
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unsigned long SGToBeXferLen; /*; to be xfer length */
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unsigned long TotalXferredLen;
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unsigned long SavedTotXLen;
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