drm/nouveau/disp/nv50-: simplify definition of overlay channels

Introduces a new method of defining channels available from the display,
common to all channel types, allowing for more flexibility in available
channel types/counts, and reducing the amount of boiler-plate required.

This will be required to support Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild

@@ -96,7 +96,6 @@ nvkm-y += nvkm/engine/disp/coregp102.o
 nvkm-y += nvkm/engine/disp/ovlynv50.o
 nvkm-y += nvkm/engine/disp/ovlyg84.o
 nvkm-y += nvkm/engine/disp/ovlygt200.o
-nvkm-y += nvkm/engine/disp/ovlygt215.o
 nvkm-y += nvkm/engine/disp/ovlygf119.o
 nvkm-y += nvkm/engine/disp/ovlygk104.o
 nvkm-y += nvkm/engine/disp/ovlygp102.o

drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h

@@ -5,6 +5,7 @@
 #include <core/object.h>
 #include "nv50.h"
 struct nv50_disp_root;
+struct nv50_disp_dmac_func;
 
 struct nv50_disp_chan {
 	const struct nv50_disp_chan_func *func;
@@ -49,6 +50,30 @@ void nv50_disp_chan_uevent_send(struct nv50_disp *, int);
 
 extern const struct nvkm_event_func gf119_disp_chan_uevent;
 
+int nv50_disp_ovly_new_(const struct nv50_disp_dmac_func *,
+			const struct nv50_disp_chan_mthd *,
+			struct nv50_disp *, int chid,
+			const struct nvkm_oclass *, void *argv, u32 argc,
+			struct nvkm_object **);
+
+int nv50_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+		       struct nv50_disp *, struct nvkm_object **);
+
+int g84_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+		      struct nv50_disp *, struct nvkm_object **);
+
+int gt200_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+			struct nv50_disp *, struct nvkm_object **);
+
+int gf119_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+			struct nv50_disp *, struct nvkm_object **);
+
+int gk104_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+			struct nv50_disp *, struct nvkm_object **);
+
+int gp102_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+			struct nv50_disp *, struct nvkm_object **);
+
 struct nv50_disp_mthd_list {
 	u32 mthd;
 	u32 addr;
@@ -81,7 +106,6 @@ extern const struct nv50_disp_chan_mthd g84_disp_core_chan_mthd;
 extern const struct nv50_disp_mthd_list g84_disp_core_mthd_dac;
 extern const struct nv50_disp_mthd_list g84_disp_core_mthd_head;
 extern const struct nv50_disp_chan_mthd g84_disp_base_chan_mthd;
-extern const struct nv50_disp_chan_mthd g84_disp_ovly_chan_mthd;
 
 extern const struct nv50_disp_chan_mthd g94_disp_core_chan_mthd;
 
@@ -92,7 +116,7 @@ extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_pior;
 extern const struct nv50_disp_chan_mthd gf119_disp_base_chan_mthd;
 
 extern const struct nv50_disp_chan_mthd gk104_disp_core_chan_mthd;
-extern const struct nv50_disp_chan_mthd gk104_disp_ovly_chan_mthd;
+extern const struct nv50_disp_chan_mthd gk104_disp_ovly_mthd;
 
 struct nv50_disp_pioc_oclass {
 	int (*ctor)(const struct nv50_disp_chan_func *,

drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.h

@@ -55,37 +55,26 @@ int nv50_disp_base_new(const struct nv50_disp_dmac_func *,
 		       struct nv50_disp_root *, int chid,
 		       const struct nvkm_oclass *oclass, void *data, u32 size,
 		       struct nvkm_object **);
-int nv50_disp_ovly_new(const struct nv50_disp_dmac_func *,
-		       const struct nv50_disp_chan_mthd *,
-		       struct nv50_disp_root *, int chid,
-		       const struct nvkm_oclass *oclass, void *data, u32 size,
-		       struct nvkm_object **);
 
 extern const struct nv50_disp_dmac_oclass nv50_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass nv50_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass nv50_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass g84_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass g84_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass g84_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass g94_disp_core_oclass;
 
 extern const struct nv50_disp_dmac_oclass gt200_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gt200_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass gt200_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass gt215_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gt215_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass gt215_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass gf119_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gf119_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass gf119_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass gk104_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gk104_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass gk104_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass gk110_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gk110_disp_base_oclass;
@@ -98,5 +87,4 @@ extern const struct nv50_disp_dmac_oclass gp100_disp_core_oclass;
 
 extern const struct nv50_disp_dmac_oclass gp102_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gp102_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass gp102_disp_ovly_oclass;
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlyg84.c

@@ -22,9 +22,6 @@
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
 
 static const struct nv50_disp_mthd_list
 g84_disp_ovly_mthd_base = {
@@ -54,8 +51,8 @@ g84_disp_ovly_mthd_base = {
 	}
 };
 
-const struct nv50_disp_chan_mthd
+static const struct nv50_disp_chan_mthd
-g84_disp_ovly_chan_mthd = {
+g84_disp_ovly_mthd = {
 	.name = "Overlay",
 	.addr = 0x000540,
 	.prev = 0x000004,
@@ -65,13 +62,10 @@ g84_disp_ovly_chan_mthd = {
 	}
 };
 
-const struct nv50_disp_dmac_oclass
+int
-g84_disp_ovly_oclass = {
+g84_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
-	.base.oclass = G82_DISP_OVERLAY_CHANNEL_DMA,
+		  struct nv50_disp *disp, struct nvkm_object **pobject)
-	.base.minver = 0,
+{
-	.base.maxver = 0,
+	return nv50_disp_ovly_new_(&nv50_disp_dmac_func, &g84_disp_ovly_mthd,
-	.ctor = nv50_disp_ovly_new,
+				   disp, 3, oclass, argv, argc, pobject);
-	.func = &nv50_disp_dmac_func,
+}
-	.mthd = &g84_disp_ovly_chan_mthd,
-	.chid = 3,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygf119.c

@@ -22,9 +22,6 @@
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
 
 static const struct nv50_disp_mthd_list
 gf119_disp_ovly_mthd_base = {
@@ -79,7 +76,7 @@ gf119_disp_ovly_mthd_base = {
 };
 
 static const struct nv50_disp_chan_mthd
-gf119_disp_ovly_chan_mthd = {
+gf119_disp_ovly_mthd = {
 	.name = "Overlay",
 	.addr = 0x001000,
 	.prev = -0x020000,
@@ -89,13 +86,10 @@ gf119_disp_ovly_chan_mthd = {
 	}
 };
 
-const struct nv50_disp_dmac_oclass
+int
-gf119_disp_ovly_oclass = {
+gf119_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
-	.base.oclass = GF110_DISP_OVERLAY_CONTROL_DMA,
+		    struct nv50_disp *disp, struct nvkm_object **pobject)
-	.base.minver = 0,
+{
-	.base.maxver = 0,
+	return nv50_disp_ovly_new_(&gf119_disp_dmac_func, &gf119_disp_ovly_mthd,
-	.ctor = nv50_disp_ovly_new,
+				   disp, 5, oclass, argv, argc, pobject);
-	.func = &gf119_disp_dmac_func,
+}
-	.mthd = &gf119_disp_ovly_chan_mthd,
-	.chid = 5,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygk104.c

@@ -22,9 +22,6 @@
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
 
 static const struct nv50_disp_mthd_list
 gk104_disp_ovly_mthd_base = {
@@ -81,7 +78,7 @@ gk104_disp_ovly_mthd_base = {
 };
 
 const struct nv50_disp_chan_mthd
-gk104_disp_ovly_chan_mthd = {
+gk104_disp_ovly_mthd = {
 	.name = "Overlay",
 	.addr = 0x001000,
 	.prev = -0x020000,
@@ -91,13 +88,10 @@ gk104_disp_ovly_chan_mthd = {
 	}
 };
 
-const struct nv50_disp_dmac_oclass
+int
-gk104_disp_ovly_oclass = {
+gk104_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
-	.base.oclass = GK104_DISP_OVERLAY_CONTROL_DMA,
+		    struct nv50_disp *disp, struct nvkm_object **pobject)
-	.base.minver = 0,
+{
-	.base.maxver = 0,
+	return nv50_disp_ovly_new_(&gf119_disp_dmac_func, &gk104_disp_ovly_mthd,
-	.ctor = nv50_disp_ovly_new,
+				   disp, 5, oclass, argv, argc, pobject);
-	.func = &gf119_disp_dmac_func,
+}
-	.mthd = &gk104_disp_ovly_chan_mthd,
-	.chid = 5,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygp102.c

@@ -22,17 +22,11 @@
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
 
-#include <nvif/class.h>
+int
-
+gp102_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
-const struct nv50_disp_dmac_oclass
+		    struct nv50_disp *disp, struct nvkm_object **pobject)
-gp102_disp_ovly_oclass = {
+{
-	.base.oclass = GK104_DISP_OVERLAY_CONTROL_DMA,
+	return nv50_disp_ovly_new_(&gp102_disp_dmac_func, &gk104_disp_ovly_mthd,
-	.base.minver = 0,
+				   disp, 5, oclass, argv, argc, pobject);
-	.base.maxver = 0,
+}
-	.ctor = nv50_disp_ovly_new,
-	.func = &gp102_disp_dmac_func,
-	.mthd = &gk104_disp_ovly_chan_mthd,
-	.chid = 5,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt200.c

@@ -22,9 +22,6 @@
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
 
 static const struct nv50_disp_mthd_list
 gt200_disp_ovly_mthd_base = {
@@ -58,7 +55,7 @@ gt200_disp_ovly_mthd_base = {
 };
 
 static const struct nv50_disp_chan_mthd
-gt200_disp_ovly_chan_mthd = {
+gt200_disp_ovly_mthd = {
 	.name = "Overlay",
 	.addr = 0x000540,
 	.prev = 0x000004,
@@ -68,13 +65,10 @@ gt200_disp_ovly_chan_mthd = {
 	}
 };
 
-const struct nv50_disp_dmac_oclass
+int
-gt200_disp_ovly_oclass = {
+gt200_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
-	.base.oclass = GT200_DISP_OVERLAY_CHANNEL_DMA,
+		    struct nv50_disp *disp, struct nvkm_object **pobject)
-	.base.minver = 0,
+{
-	.base.maxver = 0,
+	return nv50_disp_ovly_new_(&nv50_disp_dmac_func, &gt200_disp_ovly_mthd,
-	.ctor = nv50_disp_ovly_new,
+				   disp, 3, oclass, argv, argc, pobject);
-	.func = &nv50_disp_dmac_func,
+}
-	.mthd = &gt200_disp_ovly_chan_mthd,
-	.chid = 3,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt215.c

@@ -1,38 +0,0 @@
-/*
- * Copyright 2015 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-#include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
-
-const struct nv50_disp_dmac_oclass
-gt215_disp_ovly_oclass = {
-	.base.oclass = GT214_DISP_OVERLAY_CHANNEL_DMA,
-	.base.minver = 0,
-	.base.maxver = 0,
-	.ctor = nv50_disp_ovly_new,
-	.func = &nv50_disp_dmac_func,
-	.mthd = &g84_disp_ovly_chan_mthd,
-	.chid = 3,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c

@@ -23,31 +23,28 @@
  */
 #include "dmacnv50.h"
 #include "head.h"
-#include "rootnv50.h"
 
 #include <core/client.h>
 
-#include <nvif/class.h>
 #include <nvif/cl507e.h>
 #include <nvif/unpack.h>
 
 int
-nv50_disp_ovly_new(const struct nv50_disp_dmac_func *func,
+nv50_disp_ovly_new_(const struct nv50_disp_dmac_func *func,
-		   const struct nv50_disp_chan_mthd *mthd,
+		    const struct nv50_disp_chan_mthd *mthd,
-		   struct nv50_disp_root *root, int chid,
+		    struct nv50_disp *disp, int chid,
-		   const struct nvkm_oclass *oclass, void *data, u32 size,
+		    const struct nvkm_oclass *oclass, void *argv, u32 argc,
-		   struct nvkm_object **pobject)
+		    struct nvkm_object **pobject)
 {
 	union {
 		struct nv50_disp_overlay_channel_dma_v0 v0;
-	} *args = data;
+	} *args = argv;
 	struct nvkm_object *parent = oclass->parent;
-	struct nv50_disp *disp = root->disp;
 	int head, ret = -ENOSYS;
 	u64 push;
 
-	nvif_ioctl(parent, "create disp overlay channel dma size %d\n", size);
+	nvif_ioctl(parent, "create disp overlay channel dma size %d\n", argc);
-	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
+	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
 		nvif_ioctl(parent, "create disp overlay channel dma vers %d "
 				   "pushbuf %016llx head %d\n",
 			   args->v0.version, args->v0.pushbuf, args->v0.head);
@@ -91,7 +88,7 @@ nv50_disp_ovly_mthd_base = {
 };
 
 static const struct nv50_disp_chan_mthd
-nv50_disp_ovly_chan_mthd = {
+nv50_disp_ovly_mthd = {
 	.name = "Overlay",
 	.addr = 0x000540,
 	.prev = 0x000004,
@@ -101,13 +98,10 @@ nv50_disp_ovly_chan_mthd = {
 	}
 };
 
-const struct nv50_disp_dmac_oclass
+int
-nv50_disp_ovly_oclass = {
+nv50_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
-	.base.oclass = NV50_DISP_OVERLAY_CHANNEL_DMA,
+		   struct nv50_disp *disp, struct nvkm_object **pobject)
-	.base.minver = 0,
+{
-	.base.maxver = 0,
+	return nv50_disp_ovly_new_(&nv50_disp_dmac_func, &nv50_disp_ovly_mthd,
-	.ctor = nv50_disp_ovly_new,
+				   disp, 3, oclass, argv, argc, pobject);
-	.func = &nv50_disp_dmac_func,
+}
-	.mthd = &nv50_disp_ovly_chan_mthd,
-	.chid = 3,
-};

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c

@@ -31,12 +31,15 @@ g84_disp_root = {
 	.dmac = {
 		&g84_disp_core_oclass,
 		&g84_disp_base_oclass,
-		&g84_disp_ovly_oclass,
 	},
 	.pioc = {
 		&g84_disp_oimm_oclass,
 		&g84_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,G82_DISP_OVERLAY_CHANNEL_DMA},  g84_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c

@@ -31,12 +31,15 @@ g94_disp_root = {
 	.dmac = {
 		&g94_disp_core_oclass,
 		&gt200_disp_base_oclass,
-		&gt200_disp_ovly_oclass,
 	},
 	.pioc = {
 		&g84_disp_oimm_oclass,
 		&g84_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c

@@ -31,12 +31,15 @@ gf119_disp_root = {
 	.dmac = {
 		&gf119_disp_core_oclass,
 		&gf119_disp_base_oclass,
-		&gf119_disp_ovly_oclass,
 	},
 	.pioc = {
 		&gf119_disp_oimm_oclass,
 		&gf119_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,GF110_DISP_OVERLAY_CONTROL_DMA}, gf119_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c

@@ -31,12 +31,15 @@ gk104_disp_root = {
 	.dmac = {
 		&gk104_disp_core_oclass,
 		&gk104_disp_base_oclass,
-		&gk104_disp_ovly_oclass,
 	},
 	.pioc = {
 		&gk104_disp_oimm_oclass,
 		&gk104_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c

@@ -31,12 +31,15 @@ gk110_disp_root = {
 	.dmac = {
 		&gk110_disp_core_oclass,
 		&gk110_disp_base_oclass,
-		&gk104_disp_ovly_oclass,
 	},
 	.pioc = {
 		&gk104_disp_oimm_oclass,
 		&gk104_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c

@@ -31,12 +31,15 @@ gm107_disp_root = {
 	.dmac = {
 		&gm107_disp_core_oclass,
 		&gk110_disp_base_oclass,
-		&gk104_disp_ovly_oclass,
 	},
 	.pioc = {
 		&gk104_disp_oimm_oclass,
 		&gk104_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c

@@ -31,12 +31,15 @@ gm200_disp_root = {
 	.dmac = {
 		&gm200_disp_core_oclass,
 		&gk110_disp_base_oclass,
-		&gk104_disp_ovly_oclass,
 	},
 	.pioc = {
 		&gk104_disp_oimm_oclass,
 		&gk104_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c

@@ -31,12 +31,15 @@ gp100_disp_root = {
 	.dmac = {
 		&gp100_disp_core_oclass,
 		&gk110_disp_base_oclass,
-		&gk104_disp_ovly_oclass,
 	},
 	.pioc = {
 		&gk104_disp_oimm_oclass,
 		&gk104_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c

@@ -31,12 +31,15 @@ gp102_disp_root = {
 	.dmac = {
 		&gp102_disp_core_oclass,
 		&gp102_disp_base_oclass,
-		&gp102_disp_ovly_oclass,
 	},
 	.pioc = {
 		&gp102_disp_oimm_oclass,
 		&gp102_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gp102_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c

@@ -31,12 +31,15 @@ gt200_disp_root = {
 	.dmac = {
 		&gt200_disp_core_oclass,
 		&gt200_disp_base_oclass,
-		&gt200_disp_ovly_oclass,
 	},
 	.pioc = {
 		&g84_disp_oimm_oclass,
 		&g84_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c

@@ -31,12 +31,15 @@ gt215_disp_root = {
 	.dmac = {
 		&gt215_disp_core_oclass,
 		&gt215_disp_base_oclass,
-		&gt215_disp_ovly_oclass,
 	},
 	.pioc = {
 		&gt215_disp_oimm_oclass,
 		&gt215_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA},   g84_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c

@@ -288,6 +288,15 @@ nv50_disp_root_pioc_new_(const struct nvkm_oclass *oclass,
 			    sclass->chid.user, oclass, data, size, pobject);
 }
 
+static int
+nv50_disp_root_child_new_(const struct nvkm_oclass *oclass,
+			  void *argv, u32 argc, struct nvkm_object **pobject)
+{
+	struct nv50_disp *disp = nv50_disp_root(oclass->parent)->disp;
+	const struct nv50_disp_user *user = oclass->priv;
+	return user->ctor(oclass, argv, argc, disp, pobject);
+}
+
 static int
 nv50_disp_root_child_get_(struct nvkm_object *object, int index,
 			  struct nvkm_oclass *sclass)
@@ -310,6 +319,15 @@ nv50_disp_root_child_get_(struct nvkm_object *object, int index,
 		return 0;
 	}
 
+	index -= ARRAY_SIZE(root->func->pioc);
+
+	if (root->func->user[index].ctor) {
+		sclass->base = root->func->user[index].base;
+		sclass->priv = root->func->user + index;
+		sclass->ctor = nv50_disp_root_child_new_;
+		return 0;
+	}
+
 	return -EINVAL;
 }
 
@@ -351,12 +369,15 @@ nv50_disp_root = {
 	.dmac = {
 		&nv50_disp_core_oclass,
 		&nv50_disp_base_oclass,
-		&nv50_disp_ovly_oclass,
 	},
 	.pioc = {
 		&nv50_disp_oimm_oclass,
 		&nv50_disp_curs_oclass,
 	},
+	.user = {
+		{{0,0,NV50_DISP_OVERLAY_CHANNEL_DMA}, nv50_disp_ovly_new },
+		{}
+	},
 };
 
 static int

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h

@@ -13,8 +13,13 @@ struct nv50_disp_root {
 };
 
 struct nv50_disp_root_func {
-	const struct nv50_disp_dmac_oclass *dmac[3];
+	const struct nv50_disp_dmac_oclass *dmac[2];
 	const struct nv50_disp_pioc_oclass *pioc[2];
+	struct nv50_disp_user {
+		struct nvkm_sclass base;
+		int (*ctor)(const struct nvkm_oclass *, void *argv, u32 argc,
+			    struct nv50_disp *, struct nvkm_object **);
+	} user[];
 };
 
 int  nv50_disp_root_new_(const struct nv50_disp_root_func *, struct nvkm_disp *,