drm/i915: disable PCH ports if needed when disabling a CRTC
Disable any PCH ports associated with a pipe when disabling it. This should prevent transcoder disable failures due to ports still being on. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: introduce *_PIPE_ENABLED() macro] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Jesse Barnes
Chris Wilson
Родитель
bed636abea
Коммит
47a05eca72
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@ -1440,6 +1440,7 @@
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#define LVDS_PORT_EN (1 << 31)
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/* Selects pipe B for LVDS data. Must be set on pre-965. */
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#define LVDS_PIPEB_SELECT (1 << 30)
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#define LVDS_PIPE_MASK (1 << 30)
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/* LVDS dithering flag on 965/g4x platform */
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#define LVDS_ENABLE_DITHER (1 << 25)
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/* LVDS sync polarity flags. Set to invert (i.e. negative) */
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@ -1479,6 +1480,9 @@
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#define LVDS_B0B3_POWER_DOWN (0 << 2)
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#define LVDS_B0B3_POWER_UP (3 << 2)
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#define LVDS_PIPE_ENABLED(V, P) \
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(((V) & (LVDS_PIPE_MASK | LVDS_PORT_EN)) == ((P) << 30 | LVDS_PORT_EN))
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/* Video Data Island Packet control */
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#define VIDEO_DIP_DATA 0x61178
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#define VIDEO_DIP_CTL 0x61170
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@ -2067,6 +2071,10 @@
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#define DP_PORT_EN (1 << 31)
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#define DP_PIPEB_SELECT (1 << 30)
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#define DP_PIPE_MASK (1 << 30)
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#define DP_PIPE_ENABLED(V, P) \
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(((V) & (DP_PIPE_MASK | DP_PORT_EN)) == ((P) << 30 | DP_PORT_EN))
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/* Link training mode - select a suitable mode for each stage */
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#define DP_LINK_TRAIN_PAT_1 (0 << 28)
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@ -3180,11 +3188,15 @@
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#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
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#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
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#define ADPA_PIPE_ENABLED(V, P) \
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(((V) & (ADPA_TRANS_SELECT_MASK | ADPA_DAC_ENABLE)) == ((P) << 30 | ADPA_DAC_ENABLE))
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/* or SDVOB */
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#define HDMIB 0xe1140
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#define PORT_ENABLE (1 << 31)
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#define TRANSCODER_A (0)
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#define TRANSCODER_B (1 << 30)
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#define TRANSCODER_MASK (1 << 30)
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#define COLOR_FORMAT_8bpc (0)
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#define COLOR_FORMAT_12bpc (3 << 26)
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#define SDVOB_HOTPLUG_ENABLE (1 << 23)
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@ -3200,6 +3212,9 @@
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#define HSYNC_ACTIVE_HIGH (1 << 3)
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#define PORT_DETECTED (1 << 2)
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#define HDMI_PIPE_ENABLED(V, P) \
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(((V) & (TRANSCODER_MASK | PORT_ENABLE)) == ((P) << 30 | PORT_ENABLE))
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/* PCH SDVOB multiplex with HDMIB */
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#define PCH_SDVOB HDMIB
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@ -1270,12 +1270,8 @@ static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
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static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe, int reg)
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{
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u32 val;
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u32 sel_pipe;
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val = I915_READ(reg);
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sel_pipe = (val & DP_PIPEB_SELECT) >> 30;
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WARN((val & DP_PORT_EN) && sel_pipe == pipe,
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u32 val = I915_READ(reg);
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WARN(DP_PIPE_ENABLED(val, pipe),
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"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
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reg, pipe_name(pipe));
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}
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@ -1283,12 +1279,8 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
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static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe, int reg)
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{
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u32 val;
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u32 sel_pipe;
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val = I915_READ(reg);
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sel_pipe = (val & TRANSCODER_B) >> 30;
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WARN((val & PORT_ENABLE) && sel_pipe == pipe,
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u32 val = I915_READ(reg);
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WARN(HDMI_PIPE_ENABLED(val, pipe),
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"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
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reg, pipe_name(pipe));
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}
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@ -1298,7 +1290,6 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
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{
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int reg;
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u32 val;
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u32 sel_pipe;
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assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
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assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
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@ -1306,15 +1297,13 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
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reg = PCH_ADPA;
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val = I915_READ(reg);
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sel_pipe = (val & ADPA_TRANS_B_SELECT) >> 30;
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WARN(sel_pipe == pipe && (val & ADPA_DAC_ENABLE),
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WARN(ADPA_PIPE_ENABLED(val, pipe),
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"PCH VGA enabled on transcoder %c, should be disabled\n",
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pipe_name(pipe));
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reg = PCH_LVDS;
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val = I915_READ(reg);
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sel_pipe = (val & LVDS_PIPEB_SELECT) >> 30;
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WARN(sel_pipe == pipe && (val & LVDS_PORT_EN),
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WARN(LVDS_PIPE_ENABLED(val, pipe),
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"PCH LVDS enabled on transcoder %c, should be disabled\n",
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pipe_name(pipe));
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@ -1628,6 +1617,53 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv,
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intel_wait_for_vblank(dev_priv->dev, pipe);
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}
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static void disable_pch_dp(struct drm_i915_private *dev_priv,
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enum pipe pipe, int reg)
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{
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u32 val = I915_READ(reg);
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if (DP_PIPE_ENABLED(val, pipe))
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I915_WRITE(reg, val & ~DP_PORT_EN);
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}
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static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
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enum pipe pipe, int reg)
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{
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u32 val = I915_READ(reg);
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if (HDMI_PIPE_ENABLED(val, pipe))
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I915_WRITE(reg, val & ~PORT_ENABLE);
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}
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/* Disable any ports connected to this transcoder */
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static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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u32 reg, val;
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val = I915_READ(PCH_PP_CONTROL);
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I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
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disable_pch_dp(dev_priv, pipe, PCH_DP_B);
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disable_pch_dp(dev_priv, pipe, PCH_DP_C);
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disable_pch_dp(dev_priv, pipe, PCH_DP_D);
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reg = PCH_ADPA;
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val = I915_READ(reg);
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if (ADPA_PIPE_ENABLED(val, pipe))
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I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
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reg = PCH_LVDS;
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val = I915_READ(reg);
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if (LVDS_PIPE_ENABLED(val, pipe)) {
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I915_WRITE(reg, val & ~LVDS_PORT_EN);
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POSTING_READ(reg);
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udelay(100);
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}
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disable_pch_hdmi(dev_priv, pipe, HDMIB);
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disable_pch_hdmi(dev_priv, pipe, HDMIC);
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disable_pch_hdmi(dev_priv, pipe, HDMID);
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}
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static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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{
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struct drm_device *dev = crtc->dev;
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@ -2864,14 +2900,12 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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ironlake_fdi_disable(crtc);
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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temp = I915_READ(PCH_LVDS);
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if (temp & LVDS_PORT_EN) {
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I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
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POSTING_READ(PCH_LVDS);
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udelay(100);
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}
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}
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/* This is a horrible layering violation; we should be doing this in
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* the connector/encoder ->prepare instead, but we don't always have
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* enough information there about the config to know whether it will
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* actually be necessary or just cause undesired flicker.
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*/
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intel_disable_pch_ports(dev_priv, pipe);
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intel_disable_transcoder(dev_priv, pipe);
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