serial: Add auart driver for i.MX23/28
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
Родитель
9c2c35848c
Коммит
47d37d6f94
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@ -1595,4 +1595,19 @@ config SERIAL_PCH_UART
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This driver is for PCH(Platform controller Hub) UART of Intel EG20T
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which is an IOH(Input/Output Hub) for x86 embedded processor.
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Enabling PCH_DMA, this PCH UART works as DMA mode.
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config SERIAL_MXS_AUART
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depends on ARCH_MXS
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tristate "MXS AUART support"
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select SERIAL_CORE
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help
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This driver supports the MXS Application UART (AUART) port.
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config SERIAL_MXS_AUART_CONSOLE
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bool "MXS AUART console support"
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depends on SERIAL_MXS_AUART=y
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select SERIAL_CORE_CONSOLE
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help
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Enable a MXS AUART port to be the system console.
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endmenu
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@ -92,3 +92,4 @@ obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o
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obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o
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obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o
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obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o
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obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
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@ -0,0 +1,799 @@
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/*
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* Freescale STMP37XX/STMP378X Application UART driver
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*
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* Author: dmitry pervushin <dimka@embeddedalley.com>
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*
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* Copyright 2008-2010 Freescale Semiconductor, Inc.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/wait.h>
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#include <linux/tty.h>
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#include <linux/tty_driver.h>
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#include <linux/tty_flip.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#define MXS_AUART_PORTS 5
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#define AUART_CTRL0 0x00000000
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#define AUART_CTRL0_SET 0x00000004
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#define AUART_CTRL0_CLR 0x00000008
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#define AUART_CTRL0_TOG 0x0000000c
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#define AUART_CTRL1 0x00000010
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#define AUART_CTRL1_SET 0x00000014
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#define AUART_CTRL1_CLR 0x00000018
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#define AUART_CTRL1_TOG 0x0000001c
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#define AUART_CTRL2 0x00000020
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#define AUART_CTRL2_SET 0x00000024
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#define AUART_CTRL2_CLR 0x00000028
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#define AUART_CTRL2_TOG 0x0000002c
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#define AUART_LINECTRL 0x00000030
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#define AUART_LINECTRL_SET 0x00000034
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#define AUART_LINECTRL_CLR 0x00000038
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#define AUART_LINECTRL_TOG 0x0000003c
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#define AUART_LINECTRL2 0x00000040
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#define AUART_LINECTRL2_SET 0x00000044
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#define AUART_LINECTRL2_CLR 0x00000048
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#define AUART_LINECTRL2_TOG 0x0000004c
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#define AUART_INTR 0x00000050
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#define AUART_INTR_SET 0x00000054
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#define AUART_INTR_CLR 0x00000058
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#define AUART_INTR_TOG 0x0000005c
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#define AUART_DATA 0x00000060
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#define AUART_STAT 0x00000070
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#define AUART_DEBUG 0x00000080
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#define AUART_VERSION 0x00000090
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#define AUART_AUTOBAUD 0x000000a0
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#define AUART_CTRL0_SFTRST (1 << 31)
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#define AUART_CTRL0_CLKGATE (1 << 30)
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#define AUART_CTRL2_CTSEN (1 << 15)
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#define AUART_CTRL2_RTS (1 << 11)
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#define AUART_CTRL2_RXE (1 << 9)
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#define AUART_CTRL2_TXE (1 << 8)
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#define AUART_CTRL2_UARTEN (1 << 0)
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#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
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#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
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#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
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#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
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#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
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#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
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#define AUART_LINECTRL_WLEN_MASK 0x00000060
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#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
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#define AUART_LINECTRL_FEN (1 << 4)
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#define AUART_LINECTRL_STP2 (1 << 3)
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#define AUART_LINECTRL_EPS (1 << 2)
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#define AUART_LINECTRL_PEN (1 << 1)
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#define AUART_LINECTRL_BRK (1 << 0)
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#define AUART_INTR_RTIEN (1 << 22)
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#define AUART_INTR_TXIEN (1 << 21)
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#define AUART_INTR_RXIEN (1 << 20)
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#define AUART_INTR_CTSMIEN (1 << 17)
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#define AUART_INTR_RTIS (1 << 6)
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#define AUART_INTR_TXIS (1 << 5)
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#define AUART_INTR_RXIS (1 << 4)
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#define AUART_INTR_CTSMIS (1 << 1)
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#define AUART_STAT_BUSY (1 << 29)
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#define AUART_STAT_CTS (1 << 28)
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#define AUART_STAT_TXFE (1 << 27)
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#define AUART_STAT_TXFF (1 << 25)
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#define AUART_STAT_RXFE (1 << 24)
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#define AUART_STAT_OERR (1 << 19)
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#define AUART_STAT_BERR (1 << 18)
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#define AUART_STAT_PERR (1 << 17)
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#define AUART_STAT_FERR (1 << 16)
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static struct uart_driver auart_driver;
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struct mxs_auart_port {
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struct uart_port port;
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unsigned int flags;
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unsigned int ctrl;
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unsigned int irq;
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struct clk *clk;
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struct device *dev;
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};
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static void mxs_auart_stop_tx(struct uart_port *u);
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#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
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static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
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{
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struct circ_buf *xmit = &s->port.state->xmit;
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while (!(readl(s->port.membase + AUART_STAT) &
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AUART_STAT_TXFF)) {
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if (s->port.x_char) {
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s->port.icount.tx++;
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writel(s->port.x_char,
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s->port.membase + AUART_DATA);
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s->port.x_char = 0;
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continue;
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}
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if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
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s->port.icount.tx++;
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writel(xmit->buf[xmit->tail],
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s->port.membase + AUART_DATA);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&s->port);
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} else
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break;
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}
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if (uart_circ_empty(&(s->port.state->xmit)))
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writel(AUART_INTR_TXIEN,
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s->port.membase + AUART_INTR_CLR);
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else
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writel(AUART_INTR_TXIEN,
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s->port.membase + AUART_INTR_SET);
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if (uart_tx_stopped(&s->port))
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mxs_auart_stop_tx(&s->port);
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}
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static void mxs_auart_rx_char(struct mxs_auart_port *s)
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{
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int flag;
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u32 stat;
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u8 c;
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c = readl(s->port.membase + AUART_DATA);
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stat = readl(s->port.membase + AUART_STAT);
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flag = TTY_NORMAL;
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s->port.icount.rx++;
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if (stat & AUART_STAT_BERR) {
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s->port.icount.brk++;
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if (uart_handle_break(&s->port))
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goto out;
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} else if (stat & AUART_STAT_PERR) {
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s->port.icount.parity++;
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} else if (stat & AUART_STAT_FERR) {
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s->port.icount.frame++;
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}
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/*
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* Mask off conditions which should be ingored.
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*/
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stat &= s->port.read_status_mask;
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if (stat & AUART_STAT_BERR) {
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flag = TTY_BREAK;
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} else if (stat & AUART_STAT_PERR)
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flag = TTY_PARITY;
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else if (stat & AUART_STAT_FERR)
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flag = TTY_FRAME;
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if (stat & AUART_STAT_OERR)
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s->port.icount.overrun++;
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if (uart_handle_sysrq_char(&s->port, c))
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goto out;
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uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
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out:
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writel(stat, s->port.membase + AUART_STAT);
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}
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static void mxs_auart_rx_chars(struct mxs_auart_port *s)
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{
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struct tty_struct *tty = s->port.state->port.tty;
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u32 stat = 0;
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for (;;) {
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stat = readl(s->port.membase + AUART_STAT);
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if (stat & AUART_STAT_RXFE)
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break;
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mxs_auart_rx_char(s);
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}
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writel(stat, s->port.membase + AUART_STAT);
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tty_flip_buffer_push(tty);
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}
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static int mxs_auart_request_port(struct uart_port *u)
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{
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return 0;
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}
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static int mxs_auart_verify_port(struct uart_port *u,
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struct serial_struct *ser)
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{
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if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
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return -EINVAL;
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return 0;
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}
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static void mxs_auart_config_port(struct uart_port *u, int flags)
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{
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}
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static const char *mxs_auart_type(struct uart_port *u)
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{
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struct mxs_auart_port *s = to_auart_port(u);
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return dev_name(s->dev);
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}
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static void mxs_auart_release_port(struct uart_port *u)
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{
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}
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static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
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{
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struct mxs_auart_port *s = to_auart_port(u);
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u32 ctrl = readl(u->membase + AUART_CTRL2);
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ctrl &= ~AUART_CTRL2_RTS;
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if (mctrl & TIOCM_RTS)
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ctrl |= AUART_CTRL2_RTS;
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s->ctrl = mctrl;
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writel(ctrl, u->membase + AUART_CTRL2);
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}
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static u32 mxs_auart_get_mctrl(struct uart_port *u)
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{
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struct mxs_auart_port *s = to_auart_port(u);
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u32 stat = readl(u->membase + AUART_STAT);
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int ctrl2 = readl(u->membase + AUART_CTRL2);
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u32 mctrl = s->ctrl;
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mctrl &= ~TIOCM_CTS;
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if (stat & AUART_STAT_CTS)
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mctrl |= TIOCM_CTS;
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if (ctrl2 & AUART_CTRL2_RTS)
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mctrl |= TIOCM_RTS;
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return mctrl;
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}
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static void mxs_auart_settermios(struct uart_port *u,
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struct ktermios *termios,
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struct ktermios *old)
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{
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u32 bm, ctrl, ctrl2, div;
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unsigned int cflag, baud;
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cflag = termios->c_cflag;
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ctrl = AUART_LINECTRL_FEN;
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ctrl2 = readl(u->membase + AUART_CTRL2);
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/* byte size */
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switch (cflag & CSIZE) {
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case CS5:
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bm = 0;
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break;
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case CS6:
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bm = 1;
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break;
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case CS7:
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bm = 2;
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break;
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case CS8:
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bm = 3;
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break;
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default:
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return;
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}
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ctrl |= AUART_LINECTRL_WLEN(bm);
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/* parity */
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if (cflag & PARENB) {
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ctrl |= AUART_LINECTRL_PEN;
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if ((cflag & PARODD) == 0)
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ctrl |= AUART_LINECTRL_EPS;
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}
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u->read_status_mask = 0;
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if (termios->c_iflag & INPCK)
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u->read_status_mask |= AUART_STAT_PERR;
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if (termios->c_iflag & (BRKINT | PARMRK))
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u->read_status_mask |= AUART_STAT_BERR;
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/*
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* Characters to ignore
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*/
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u->ignore_status_mask = 0;
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if (termios->c_iflag & IGNPAR)
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u->ignore_status_mask |= AUART_STAT_PERR;
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if (termios->c_iflag & IGNBRK) {
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u->ignore_status_mask |= AUART_STAT_BERR;
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/*
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* If we're ignoring parity and break indicators,
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* ignore overruns too (for real raw support).
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*/
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if (termios->c_iflag & IGNPAR)
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u->ignore_status_mask |= AUART_STAT_OERR;
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}
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/*
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* ignore all characters if CREAD is not set
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*/
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if (cflag & CREAD)
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ctrl2 |= AUART_CTRL2_RXE;
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else
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ctrl2 &= ~AUART_CTRL2_RXE;
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/* figure out the stop bits requested */
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if (cflag & CSTOPB)
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ctrl |= AUART_LINECTRL_STP2;
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/* figure out the hardware flow control settings */
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if (cflag & CRTSCTS)
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ctrl2 |= AUART_CTRL2_CTSEN;
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else
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ctrl2 &= ~AUART_CTRL2_CTSEN;
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/* set baud rate */
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baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
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div = u->uartclk * 32 / baud;
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ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
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ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
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writel(ctrl, u->membase + AUART_LINECTRL);
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writel(ctrl2, u->membase + AUART_CTRL2);
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}
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static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
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{
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u32 istatus, istat;
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struct mxs_auart_port *s = context;
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u32 stat = readl(s->port.membase + AUART_STAT);
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istatus = istat = readl(s->port.membase + AUART_INTR);
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if (istat & AUART_INTR_CTSMIS) {
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uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
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writel(AUART_INTR_CTSMIS,
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s->port.membase + AUART_INTR_CLR);
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istat &= ~AUART_INTR_CTSMIS;
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}
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if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
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mxs_auart_rx_chars(s);
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istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
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}
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if (istat & AUART_INTR_TXIS) {
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mxs_auart_tx_chars(s);
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istat &= ~AUART_INTR_TXIS;
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}
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writel(istatus & (AUART_INTR_RTIS
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| AUART_INTR_TXIS
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| AUART_INTR_RXIS
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| AUART_INTR_CTSMIS),
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s->port.membase + AUART_INTR_CLR);
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return IRQ_HANDLED;
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}
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static void mxs_auart_reset(struct uart_port *u)
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{
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int i;
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unsigned int reg;
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writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
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for (i = 0; i < 10000; i++) {
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reg = readl(u->membase + AUART_CTRL0);
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if (!(reg & AUART_CTRL0_SFTRST))
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break;
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udelay(3);
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}
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writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
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}
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static int mxs_auart_startup(struct uart_port *u)
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{
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struct mxs_auart_port *s = to_auart_port(u);
|
||||
|
||||
clk_enable(s->clk);
|
||||
|
||||
writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
|
||||
|
||||
writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
|
||||
|
||||
writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
|
||||
u->membase + AUART_INTR);
|
||||
|
||||
/*
|
||||
* Enable fifo so all four bytes of a DMA word are written to
|
||||
* output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
|
||||
*/
|
||||
writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mxs_auart_shutdown(struct uart_port *u)
|
||||
{
|
||||
struct mxs_auart_port *s = to_auart_port(u);
|
||||
|
||||
writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
|
||||
|
||||
writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
|
||||
|
||||
writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
|
||||
u->membase + AUART_INTR_CLR);
|
||||
|
||||
clk_disable(s->clk);
|
||||
}
|
||||
|
||||
static unsigned int mxs_auart_tx_empty(struct uart_port *u)
|
||||
{
|
||||
if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
|
||||
return TIOCSER_TEMT;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mxs_auart_start_tx(struct uart_port *u)
|
||||
{
|
||||
struct mxs_auart_port *s = to_auart_port(u);
|
||||
|
||||
/* enable transmitter */
|
||||
writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
|
||||
|
||||
mxs_auart_tx_chars(s);
|
||||
}
|
||||
|
||||
static void mxs_auart_stop_tx(struct uart_port *u)
|
||||
{
|
||||
writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
|
||||
}
|
||||
|
||||
static void mxs_auart_stop_rx(struct uart_port *u)
|
||||
{
|
||||
writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
|
||||
}
|
||||
|
||||
static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
|
||||
{
|
||||
if (ctl)
|
||||
writel(AUART_LINECTRL_BRK,
|
||||
u->membase + AUART_LINECTRL_SET);
|
||||
else
|
||||
writel(AUART_LINECTRL_BRK,
|
||||
u->membase + AUART_LINECTRL_CLR);
|
||||
}
|
||||
|
||||
static void mxs_auart_enable_ms(struct uart_port *port)
|
||||
{
|
||||
/* just empty */
|
||||
}
|
||||
|
||||
static struct uart_ops mxs_auart_ops = {
|
||||
.tx_empty = mxs_auart_tx_empty,
|
||||
.start_tx = mxs_auart_start_tx,
|
||||
.stop_tx = mxs_auart_stop_tx,
|
||||
.stop_rx = mxs_auart_stop_rx,
|
||||
.enable_ms = mxs_auart_enable_ms,
|
||||
.break_ctl = mxs_auart_break_ctl,
|
||||
.set_mctrl = mxs_auart_set_mctrl,
|
||||
.get_mctrl = mxs_auart_get_mctrl,
|
||||
.startup = mxs_auart_startup,
|
||||
.shutdown = mxs_auart_shutdown,
|
||||
.set_termios = mxs_auart_settermios,
|
||||
.type = mxs_auart_type,
|
||||
.release_port = mxs_auart_release_port,
|
||||
.request_port = mxs_auart_request_port,
|
||||
.config_port = mxs_auart_config_port,
|
||||
.verify_port = mxs_auart_verify_port,
|
||||
};
|
||||
|
||||
static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
|
||||
|
||||
#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
|
||||
static void mxs_auart_console_putchar(struct uart_port *port, int ch)
|
||||
{
|
||||
unsigned int to = 1000;
|
||||
|
||||
while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
|
||||
if (!to--)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
writel(ch, port->membase + AUART_DATA);
|
||||
}
|
||||
|
||||
static void
|
||||
auart_console_write(struct console *co, const char *str, unsigned int count)
|
||||
{
|
||||
struct mxs_auart_port *s;
|
||||
struct uart_port *port;
|
||||
unsigned int old_ctrl0, old_ctrl2;
|
||||
unsigned int to = 1000;
|
||||
|
||||
if (co->index > MXS_AUART_PORTS || co->index < 0)
|
||||
return;
|
||||
|
||||
s = auart_port[co->index];
|
||||
port = &s->port;
|
||||
|
||||
clk_enable(s->clk);
|
||||
|
||||
/* First save the CR then disable the interrupts */
|
||||
old_ctrl2 = readl(port->membase + AUART_CTRL2);
|
||||
old_ctrl0 = readl(port->membase + AUART_CTRL0);
|
||||
|
||||
writel(AUART_CTRL0_CLKGATE,
|
||||
port->membase + AUART_CTRL0_CLR);
|
||||
writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
|
||||
port->membase + AUART_CTRL2_SET);
|
||||
|
||||
uart_console_write(port, str, count, mxs_auart_console_putchar);
|
||||
|
||||
/*
|
||||
* Finally, wait for transmitter to become empty
|
||||
* and restore the TCR
|
||||
*/
|
||||
while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
|
||||
if (!to--)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
writel(old_ctrl0, port->membase + AUART_CTRL0);
|
||||
writel(old_ctrl2, port->membase + AUART_CTRL2);
|
||||
|
||||
clk_disable(s->clk);
|
||||
}
|
||||
|
||||
static void __init
|
||||
auart_console_get_options(struct uart_port *port, int *baud,
|
||||
int *parity, int *bits)
|
||||
{
|
||||
unsigned int lcr_h, quot;
|
||||
|
||||
if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
|
||||
return;
|
||||
|
||||
lcr_h = readl(port->membase + AUART_LINECTRL);
|
||||
|
||||
*parity = 'n';
|
||||
if (lcr_h & AUART_LINECTRL_PEN) {
|
||||
if (lcr_h & AUART_LINECTRL_EPS)
|
||||
*parity = 'e';
|
||||
else
|
||||
*parity = 'o';
|
||||
}
|
||||
|
||||
if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
|
||||
*bits = 7;
|
||||
else
|
||||
*bits = 8;
|
||||
|
||||
quot = ((readl(port->membase + AUART_LINECTRL)
|
||||
& AUART_LINECTRL_BAUD_DIVINT_MASK))
|
||||
>> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
|
||||
quot |= ((readl(port->membase + AUART_LINECTRL)
|
||||
& AUART_LINECTRL_BAUD_DIVFRAC_MASK))
|
||||
>> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
|
||||
if (quot == 0)
|
||||
quot = 1;
|
||||
|
||||
*baud = (port->uartclk << 2) / quot;
|
||||
}
|
||||
|
||||
static int __init
|
||||
auart_console_setup(struct console *co, char *options)
|
||||
{
|
||||
struct mxs_auart_port *s;
|
||||
int baud = 9600;
|
||||
int bits = 8;
|
||||
int parity = 'n';
|
||||
int flow = 'n';
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Check whether an invalid uart number has been specified, and
|
||||
* if so, search for the first available port that does have
|
||||
* console support.
|
||||
*/
|
||||
if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
|
||||
co->index = 0;
|
||||
s = auart_port[co->index];
|
||||
if (!s)
|
||||
return -ENODEV;
|
||||
|
||||
clk_enable(s->clk);
|
||||
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
else
|
||||
auart_console_get_options(&s->port, &baud, &parity, &bits);
|
||||
|
||||
ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
|
||||
|
||||
clk_disable(s->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct console auart_console = {
|
||||
.name = "ttyAPP",
|
||||
.write = auart_console_write,
|
||||
.device = uart_console_device,
|
||||
.setup = auart_console_setup,
|
||||
.flags = CON_PRINTBUFFER,
|
||||
.index = -1,
|
||||
.data = &auart_driver,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct uart_driver auart_driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.driver_name = "ttyAPP",
|
||||
.dev_name = "ttyAPP",
|
||||
.major = 0,
|
||||
.minor = 0,
|
||||
.nr = MXS_AUART_PORTS,
|
||||
#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
|
||||
.cons = &auart_console,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __devinit mxs_auart_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct mxs_auart_port *s;
|
||||
u32 version;
|
||||
int ret = 0;
|
||||
struct resource *r;
|
||||
|
||||
s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
|
||||
if (!s) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
s->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(s->clk)) {
|
||||
ret = PTR_ERR(s->clk);
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!r) {
|
||||
ret = -ENXIO;
|
||||
goto out_free_clk;
|
||||
}
|
||||
|
||||
s->port.mapbase = r->start;
|
||||
s->port.membase = ioremap(r->start, resource_size(r));
|
||||
s->port.ops = &mxs_auart_ops;
|
||||
s->port.iotype = UPIO_MEM;
|
||||
s->port.line = pdev->id < 0 ? 0 : pdev->id;
|
||||
s->port.fifosize = 16;
|
||||
s->port.uartclk = clk_get_rate(s->clk);
|
||||
s->port.type = PORT_IMX;
|
||||
s->port.dev = s->dev = get_device(&pdev->dev);
|
||||
|
||||
s->flags = 0;
|
||||
s->ctrl = 0;
|
||||
|
||||
s->irq = platform_get_irq(pdev, 0);
|
||||
s->port.irq = s->irq;
|
||||
ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
|
||||
if (ret)
|
||||
goto out_free_clk;
|
||||
|
||||
platform_set_drvdata(pdev, s);
|
||||
|
||||
auart_port[pdev->id] = s;
|
||||
|
||||
mxs_auart_reset(&s->port);
|
||||
|
||||
ret = uart_add_one_port(&auart_driver, &s->port);
|
||||
if (ret)
|
||||
goto out_free_irq;
|
||||
|
||||
version = readl(s->port.membase + AUART_VERSION);
|
||||
dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
|
||||
(version >> 24) & 0xff,
|
||||
(version >> 16) & 0xff, version & 0xffff);
|
||||
|
||||
return 0;
|
||||
|
||||
out_free_irq:
|
||||
auart_port[pdev->id] = NULL;
|
||||
free_irq(s->irq, s);
|
||||
out_free_clk:
|
||||
clk_put(s->clk);
|
||||
out_free:
|
||||
kfree(s);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit mxs_auart_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mxs_auart_port *s = platform_get_drvdata(pdev);
|
||||
|
||||
uart_remove_one_port(&auart_driver, &s->port);
|
||||
|
||||
auart_port[pdev->id] = NULL;
|
||||
|
||||
clk_put(s->clk);
|
||||
free_irq(s->irq, s);
|
||||
kfree(s);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver mxs_auart_driver = {
|
||||
.probe = mxs_auart_probe,
|
||||
.remove = __devexit_p(mxs_auart_remove),
|
||||
.driver = {
|
||||
.name = "mxs-auart",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init mxs_auart_init(void)
|
||||
{
|
||||
int r;
|
||||
|
||||
r = uart_register_driver(&auart_driver);
|
||||
if (r)
|
||||
goto out;
|
||||
|
||||
r = platform_driver_register(&mxs_auart_driver);
|
||||
if (r)
|
||||
goto out_err;
|
||||
|
||||
return 0;
|
||||
out_err:
|
||||
uart_unregister_driver(&auart_driver);
|
||||
out:
|
||||
return r;
|
||||
}
|
||||
|
||||
static void __exit mxs_auart_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&mxs_auart_driver);
|
||||
uart_unregister_driver(&auart_driver);
|
||||
}
|
||||
|
||||
module_init(mxs_auart_init);
|
||||
module_exit(mxs_auart_exit);
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("Freescale MXS application uart driver");
|
||||
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