drm/radeon: dpm updates for KV/KB
- Use vddc/sclk dep table for voltage if available - Fix UVD DPM setup - Patch voltage tables properly for non-UVD blocks - Fix DPM + UVD/VCE on Mullins Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
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47f5c74616
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@ -546,6 +546,52 @@ static int kv_set_divider_value(struct radeon_device *rdev,
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return 0;
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}
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static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev,
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struct sumo_vid_mapping_table *vid_mapping_table,
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u32 vid_2bit)
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{
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struct radeon_clock_voltage_dependency_table *vddc_sclk_table =
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&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
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u32 i;
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if (vddc_sclk_table && vddc_sclk_table->count) {
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if (vid_2bit < vddc_sclk_table->count)
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return vddc_sclk_table->entries[vid_2bit].v;
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else
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return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
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} else {
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for (i = 0; i < vid_mapping_table->num_entries; i++) {
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if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
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return vid_mapping_table->entries[i].vid_7bit;
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}
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return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
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}
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}
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static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev,
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struct sumo_vid_mapping_table *vid_mapping_table,
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u32 vid_7bit)
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{
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struct radeon_clock_voltage_dependency_table *vddc_sclk_table =
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&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
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u32 i;
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if (vddc_sclk_table && vddc_sclk_table->count) {
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for (i = 0; i < vddc_sclk_table->count; i++) {
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if (vddc_sclk_table->entries[i].v == vid_7bit)
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return i;
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}
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return vddc_sclk_table->count - 1;
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} else {
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for (i = 0; i < vid_mapping_table->num_entries; i++) {
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if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
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return vid_mapping_table->entries[i].vid_2bit;
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}
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return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
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}
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}
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static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
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u16 voltage)
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{
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@ -556,9 +602,9 @@ static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
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u32 vid_2bit)
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{
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struct kv_power_info *pi = kv_get_pi(rdev);
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u32 vid_8bit = sumo_convert_vid2_to_vid7(rdev,
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&pi->sys_info.vid_mapping_table,
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vid_2bit);
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u32 vid_8bit = kv_convert_vid2_to_vid7(rdev,
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&pi->sys_info.vid_mapping_table,
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vid_2bit);
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return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
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}
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@ -1362,13 +1408,20 @@ static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
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struct radeon_uvd_clock_voltage_dependency_table *table =
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&rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
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int ret;
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u32 mask;
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if (!gate) {
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if (!pi->caps_uvd_dpm || table->count || pi->caps_stable_p_state)
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if (table->count)
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pi->uvd_boot_level = table->count - 1;
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else
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pi->uvd_boot_level = 0;
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if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
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mask = 1 << pi->uvd_boot_level;
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} else {
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mask = 0x1f;
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}
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ret = kv_copy_bytes_to_smc(rdev,
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pi->dpm_table_start +
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offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
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@ -1377,11 +1430,9 @@ static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
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if (ret)
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return ret;
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if (!pi->caps_uvd_dpm ||
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pi->caps_stable_p_state)
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kv_send_msg_to_smc_with_parameter(rdev,
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PPSMC_MSG_UVDDPM_SetEnabledMask,
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(1 << pi->uvd_boot_level));
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kv_send_msg_to_smc_with_parameter(rdev,
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PPSMC_MSG_UVDDPM_SetEnabledMask,
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mask);
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}
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return kv_enable_uvd_dpm(rdev, !gate);
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@ -1812,6 +1863,8 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
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return ret;
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}
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kv_update_sclk_t(rdev);
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if (rdev->family == CHIP_MULLINS)
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kv_enable_nb_dpm(rdev);
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}
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} else {
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if (pi->enable_dpm) {
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@ -1901,14 +1954,41 @@ static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
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static void kv_patch_voltage_values(struct radeon_device *rdev)
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{
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int i;
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struct radeon_uvd_clock_voltage_dependency_table *table =
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struct radeon_uvd_clock_voltage_dependency_table *uvd_table =
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&rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
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struct radeon_vce_clock_voltage_dependency_table *vce_table =
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&rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
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struct radeon_clock_voltage_dependency_table *samu_table =
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&rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
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struct radeon_clock_voltage_dependency_table *acp_table =
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&rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
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if (table->count) {
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for (i = 0; i < table->count; i++)
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table->entries[i].v =
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if (uvd_table->count) {
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for (i = 0; i < uvd_table->count; i++)
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uvd_table->entries[i].v =
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kv_convert_8bit_index_to_voltage(rdev,
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table->entries[i].v);
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uvd_table->entries[i].v);
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}
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if (vce_table->count) {
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for (i = 0; i < vce_table->count; i++)
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vce_table->entries[i].v =
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kv_convert_8bit_index_to_voltage(rdev,
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vce_table->entries[i].v);
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}
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if (samu_table->count) {
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for (i = 0; i < samu_table->count; i++)
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samu_table->entries[i].v =
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kv_convert_8bit_index_to_voltage(rdev,
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samu_table->entries[i].v);
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}
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if (acp_table->count) {
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for (i = 0; i < acp_table->count; i++)
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acp_table->entries[i].v =
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kv_convert_8bit_index_to_voltage(rdev,
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acp_table->entries[i].v);
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}
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}
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@ -2253,9 +2333,9 @@ static void kv_init_graphics_levels(struct radeon_device *rdev)
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break;
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kv_set_divider_value(rdev, i, table->entries[i].clk);
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vid_2bit = sumo_convert_vid7_to_vid2(rdev,
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&pi->sys_info.vid_mapping_table,
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table->entries[i].v);
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vid_2bit = kv_convert_vid7_to_vid2(rdev,
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&pi->sys_info.vid_mapping_table,
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table->entries[i].v);
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kv_set_vid(rdev, i, vid_2bit);
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kv_set_at(rdev, i, pi->at[i]);
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kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
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@ -2631,9 +2711,6 @@ int kv_dpm_init(struct radeon_device *rdev)
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pi->sram_end = SMC_RAM_END;
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if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
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pi->high_voltage_t = 4001;
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pi->enable_nb_dpm = true;
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pi->caps_power_containment = true;
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