Merge branch 'topic/ppc-kvm' into next
Merge in some commits we're sharing with the kvm-ppc tree.
This commit is contained in:
Michael Ellerman
Коммит
481c63acba
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@ -134,4 +134,7 @@ unsigned long prepare_ftrace_return(unsigned long parent, unsigned long ip);
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void pnv_power9_force_smt4_catch(void);
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void pnv_power9_force_smt4_release(void);
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void tm_enable(void);
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void tm_disable(void);
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void tm_abort(uint8_t cause);
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#endif /* _ASM_POWERPC_ASM_PROTOTYPES_H */
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@ -51,4 +51,11 @@ extern void radix__flush_tlb_all(void);
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extern void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,
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unsigned long address);
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extern void radix__flush_tlb_lpid_page(unsigned int lpid,
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unsigned long addr,
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unsigned long page_size);
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extern void radix__flush_pwc_lpid(unsigned int lpid);
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extern void radix__local_flush_tlb_lpid(unsigned int lpid);
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extern void radix__local_flush_tlb_lpid_guest(unsigned int lpid);
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#endif
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@ -146,6 +146,12 @@
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#define MSR_64BIT 0
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#endif
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/* Condition Register related */
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#define CR0_SHIFT 28
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#define CR0_MASK 0xF
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#define CR0_TBEGIN_FAILURE (0x2 << 28) /* 0b0010 */
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/* Power Management - Processor Stop Status and Control Register Fields */
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#define PSSCR_RL_MASK 0x0000000F /* Requested Level */
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#define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */
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@ -239,13 +245,27 @@
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#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
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#define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */
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#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */
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#define TEXASR_ABORT __MASK(63-31) /* terminated by tabort or treclaim */
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#define TEXASR_SUSP __MASK(63-32) /* tx failed in suspended state */
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#define TEXASR_HV __MASK(63-34) /* MSR[HV] when failure occurred */
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#define TEXASR_PR __MASK(63-35) /* MSR[PR] when failure occurred */
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#define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */
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#define TEXASR_EXACT __MASK(63-37) /* TFIAR value is exact */
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#define TEXASR_FC_LG (63 - 7) /* Failure Code */
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#define TEXASR_AB_LG (63 - 31) /* Abort */
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#define TEXASR_SU_LG (63 - 32) /* Suspend */
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#define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/
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#define TEXASR_PR_LG (63 - 35) /* Privilege level */
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#define TEXASR_FS_LG (63 - 36) /* failure summary */
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#define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */
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#define TEXASR_ROT_LG (63 - 38) /* ROT bit */
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#define TEXASR_ABORT __MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */
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#define TEXASR_SUSP __MASK(TEXASR_SU_LG) /* tx failed in suspended state */
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#define TEXASR_HV __MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */
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#define TEXASR_PR __MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */
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#define TEXASR_FS __MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */
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#define TEXASR_EXACT __MASK(TEXASR_EX_LG) /* TFIAR value is exact */
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#define TEXASR_ROT __MASK(TEXASR_ROT_LG)
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#define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG)
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#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
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#define SPRN_TIDR 144 /* Thread ID register */
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#define SPRN_CTRLF 0x088
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#define SPRN_CTRLT 0x098
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@ -10,12 +10,10 @@
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#ifndef __ASSEMBLY__
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extern void tm_enable(void);
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extern void tm_reclaim(struct thread_struct *thread,
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uint8_t cause);
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extern void tm_reclaim_current(uint8_t cause);
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extern void tm_recheckpoint(struct thread_struct *thread);
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extern void tm_abort(uint8_t cause);
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extern void tm_save_sprs(struct thread_struct *thread);
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extern void tm_restore_sprs(struct thread_struct *thread);
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@ -25,6 +25,7 @@
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#include <linux/kvm_para.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/pagemap.h>
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#include <asm/reg.h>
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#include <asm/sections.h>
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@ -672,14 +673,13 @@ static void kvm_use_magic_page(void)
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{
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u32 *p;
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u32 *start, *end;
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u32 tmp;
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u32 features;
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/* Tell the host to map the magic page to -4096 on all CPUs */
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on_each_cpu(kvm_map_magic_page, &features, 1);
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/* Quick self-test to see if the mapping works */
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if (__get_user(tmp, (u32*)KVM_MAGIC_PAGE)) {
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if (!fault_in_pages_readable((const char *)KVM_MAGIC_PAGE, sizeof(u32))) {
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kvm_patching_worked = false;
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return;
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}
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@ -154,6 +154,7 @@ unsigned long msr_check_and_set(unsigned long bits)
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return newmsr;
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}
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EXPORT_SYMBOL_GPL(msr_check_and_set);
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void __msr_check_and_clear(unsigned long bits)
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{
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@ -12,6 +12,7 @@
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#include <asm/ptrace.h>
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#include <asm/reg.h>
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#include <asm/bug.h>
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#include <asm/export.h>
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#ifdef CONFIG_VSX
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/* See fpu.S, this is borrowed from there */
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@ -55,6 +56,16 @@ _GLOBAL(tm_enable)
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or r4, r4, r3
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mtmsrd r4
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1: blr
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EXPORT_SYMBOL_GPL(tm_enable);
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_GLOBAL(tm_disable)
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mfmsr r4
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li r3, MSR_TM >> 32
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sldi r3, r3, 32
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andc r4, r4, r3
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mtmsrd r4
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blr
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EXPORT_SYMBOL_GPL(tm_disable);
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_GLOBAL(tm_save_sprs)
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mfspr r0, SPRN_TFHAR
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@ -78,6 +89,7 @@ _GLOBAL(tm_restore_sprs)
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_GLOBAL(tm_abort)
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TABORT(R3)
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blr
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EXPORT_SYMBOL_GPL(tm_abort);
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/* void tm_reclaim(struct thread_struct *thread,
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* uint8_t cause)
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@ -64,6 +64,7 @@
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#include <asm/trace.h>
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#include <asm/ps3.h>
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#include <asm/pte-walk.h>
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#include <asm/asm-prototypes.h>
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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@ -118,6 +118,53 @@ static inline void __tlbie_pid(unsigned long pid, unsigned long ric)
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static inline void __tlbiel_lpid(unsigned long lpid, int set,
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unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = PPC_BIT(52); /* IS = 2 */
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rb |= set << PPC_BITLSHIFT(51);
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rs = 0; /* LPID comes from LPIDR */
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prs = 0; /* partition scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(lpid, 1, rb, rs, ric, prs, r);
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}
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static inline void __tlbie_lpid(unsigned long lpid, unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = PPC_BIT(52); /* IS = 2 */
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rs = lpid;
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prs = 0; /* partition scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
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}
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static inline void __tlbiel_lpid_guest(unsigned long lpid, int set,
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unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = PPC_BIT(52); /* IS = 2 */
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rb |= set << PPC_BITLSHIFT(51);
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rs = 0; /* LPID comes from LPIDR */
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prs = 1; /* process scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(lpid, 1, rb, rs, ric, prs, r);
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}
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static inline void __tlbiel_va(unsigned long va, unsigned long pid,
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unsigned long ap, unsigned long ric)
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{
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@ -150,6 +197,22 @@ static inline void __tlbie_va(unsigned long va, unsigned long pid,
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static inline void __tlbie_lpid_va(unsigned long va, unsigned long lpid,
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unsigned long ap, unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = va & ~(PPC_BITMASK(52, 63));
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rb |= ap << PPC_BITLSHIFT(58);
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rs = lpid;
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prs = 0; /* partition scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
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}
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static inline void fixup_tlbie(void)
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{
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unsigned long pid = 0;
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@ -161,6 +224,16 @@ static inline void fixup_tlbie(void)
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}
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}
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static inline void fixup_tlbie_lpid(unsigned long lpid)
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{
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unsigned long va = ((1UL << 52) - 1);
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) {
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asm volatile("ptesync": : :"memory");
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__tlbie_lpid_va(va, lpid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB);
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}
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}
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/*
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* We use 128 set in radix mode and 256 set in hpt mode.
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*/
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@ -214,6 +287,86 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
|
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static inline void _tlbiel_lpid(unsigned long lpid, unsigned long ric)
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{
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int set;
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|
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VM_BUG_ON(mfspr(SPRN_LPID) != lpid);
|
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asm volatile("ptesync": : :"memory");
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|
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/*
|
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* Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL,
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* also flush the entire Page Walk Cache.
|
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*/
|
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__tlbiel_lpid(lpid, 0, ric);
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/* For PWC, only one flush is needed */
|
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if (ric == RIC_FLUSH_PWC) {
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asm volatile("ptesync": : :"memory");
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return;
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}
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/* For the remaining sets, just flush the TLB */
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for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
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__tlbiel_lpid(lpid, set, RIC_FLUSH_TLB);
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asm volatile("ptesync": : :"memory");
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asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
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}
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static inline void _tlbie_lpid(unsigned long lpid, unsigned long ric)
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{
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asm volatile("ptesync": : :"memory");
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|
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/*
|
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* Workaround the fact that the "ric" argument to __tlbie_pid
|
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* must be a compile-time contraint to match the "i" constraint
|
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* in the asm statement.
|
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*/
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switch (ric) {
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case RIC_FLUSH_TLB:
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__tlbie_lpid(lpid, RIC_FLUSH_TLB);
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break;
|
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case RIC_FLUSH_PWC:
|
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__tlbie_lpid(lpid, RIC_FLUSH_PWC);
|
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break;
|
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case RIC_FLUSH_ALL:
|
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default:
|
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__tlbie_lpid(lpid, RIC_FLUSH_ALL);
|
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}
|
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fixup_tlbie_lpid(lpid);
|
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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|
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static inline void _tlbiel_lpid_guest(unsigned long lpid, unsigned long ric)
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{
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int set;
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VM_BUG_ON(mfspr(SPRN_LPID) != lpid);
|
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asm volatile("ptesync": : :"memory");
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|
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/*
|
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* Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL,
|
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* also flush the entire Page Walk Cache.
|
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*/
|
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__tlbiel_lpid_guest(lpid, 0, ric);
|
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|
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/* For PWC, only one flush is needed */
|
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if (ric == RIC_FLUSH_PWC) {
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asm volatile("ptesync": : :"memory");
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return;
|
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}
|
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|
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/* For the remaining sets, just flush the TLB */
|
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for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
|
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__tlbiel_lpid_guest(lpid, set, RIC_FLUSH_TLB);
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|
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asm volatile("ptesync": : :"memory");
|
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}
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|
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|
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static inline void __tlbiel_va_range(unsigned long start, unsigned long end,
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unsigned long pid, unsigned long page_size,
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unsigned long psize)
|
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|
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@ -268,6 +421,17 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid,
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
|
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}
|
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|
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static inline void _tlbie_lpid_va(unsigned long va, unsigned long lpid,
|
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unsigned long psize, unsigned long ric)
|
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{
|
||||
unsigned long ap = mmu_get_ap(psize);
|
||||
|
||||
asm volatile("ptesync": : :"memory");
|
||||
__tlbie_lpid_va(va, lpid, ap, ric);
|
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fixup_tlbie_lpid(lpid);
|
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
|
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}
|
||||
|
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static inline void _tlbie_va_range(unsigned long start, unsigned long end,
|
||||
unsigned long pid, unsigned long page_size,
|
||||
unsigned long psize, bool also_pwc)
|
||||
|
|
@ -534,6 +698,49 @@ static int radix_get_mmu_psize(int page_size)
|
|||
return psize;
|
||||
}
|
||||
|
||||
/*
|
||||
* Flush partition scoped LPID address translation for all CPUs.
|
||||
*/
|
||||
void radix__flush_tlb_lpid_page(unsigned int lpid,
|
||||
unsigned long addr,
|
||||
unsigned long page_size)
|
||||
{
|
||||
int psize = radix_get_mmu_psize(page_size);
|
||||
|
||||
_tlbie_lpid_va(addr, lpid, psize, RIC_FLUSH_TLB);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(radix__flush_tlb_lpid_page);
|
||||
|
||||
/*
|
||||
* Flush partition scoped PWC from LPID for all CPUs.
|
||||
*/
|
||||
void radix__flush_pwc_lpid(unsigned int lpid)
|
||||
{
|
||||
_tlbie_lpid(lpid, RIC_FLUSH_PWC);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(radix__flush_pwc_lpid);
|
||||
|
||||
/*
|
||||
* Flush partition scoped translations from LPID (=LPIDR)
|
||||
*/
|
||||
void radix__local_flush_tlb_lpid(unsigned int lpid)
|
||||
{
|
||||
_tlbiel_lpid(lpid, RIC_FLUSH_ALL);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(radix__local_flush_tlb_lpid);
|
||||
|
||||
/*
|
||||
* Flush process scoped translations from LPID (=LPIDR).
|
||||
* Important difference, the guest normally manages its own translations,
|
||||
* but some cases e.g., vCPU CPU migration require KVM to flush.
|
||||
*/
|
||||
void radix__local_flush_tlb_lpid_guest(unsigned int lpid)
|
||||
{
|
||||
_tlbiel_lpid_guest(lpid, RIC_FLUSH_ALL);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(radix__local_flush_tlb_lpid_guest);
|
||||
|
||||
|
||||
static void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsigned long start,
|
||||
unsigned long end, int psize);
|
||||
|
||||
|
|
|
|||
|
|
@ -7,9 +7,8 @@
|
|||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
#include <asm/ppc-opcode.h>
|
||||
#include <asm/reg.h>
|
||||
|
||||
#define CR0_SHIFT 28
|
||||
#define CR0_MASK 0xF
|
||||
/*
|
||||
* Copy/paste instructions:
|
||||
*
|
||||
|
|
|
|||
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