Add fs_enet ethernet network driver, for several embedded platforms.
This commit is contained in:
Pantelis Antoniou
Jeff Garzik
Родитель
d8840ac907
Коммит
48257c4f16
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@ -1775,6 +1775,7 @@ config NE_H8300
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controller on the Renesas H8/300 processor.
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source "drivers/net/fec_8xx/Kconfig"
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source "drivers/net/fs_enet/Kconfig"
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endmenu
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@ -203,3 +203,6 @@ obj-$(CONFIG_IRDA) += irda/
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obj-$(CONFIG_ETRAX_ETHERNET) += cris/
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obj-$(CONFIG_NETCONSOLE) += netconsole.o
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obj-$(CONFIG_FS_ENET) += fs_enet/
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@ -0,0 +1,20 @@
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config FS_ENET
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tristate "Freescale Ethernet Driver"
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depends on NET_ETHERNET && (CPM1 || CPM2)
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select MII
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config FS_ENET_HAS_SCC
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bool "Chip has an SCC usable for ethernet"
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depends on FS_ENET && (CPM1 || CPM2)
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default y
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config FS_ENET_HAS_FCC
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bool "Chip has an FCC usable for ethernet"
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depends on FS_ENET && CPM2
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default y
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config FS_ENET_HAS_FEC
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bool "Chip has an FEC usable for ethernet"
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depends on FS_ENET && CPM1
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default y
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@ -0,0 +1,10 @@
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#
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# Makefile for the Freescale Ethernet controllers
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#
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obj-$(CONFIG_FS_ENET) += fs_enet.o
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obj-$(CONFIG_8xx) += mac-fec.o mac-scc.o
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obj-$(CONFIG_8260) += mac-fcc.o
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fs_enet-objs := fs_enet-main.o fs_enet-mii.o mii-bitbang.o mii-fixed.o
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -0,0 +1,507 @@
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/*
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* Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
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*
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* Copyright (c) 2003 Intracom S.A.
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* by Pantelis Antoniou <panto@intracom.gr>
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*
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* 2005 (c) MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* Heavily based on original FEC driver by Dan Malek <dan@embeddededge.com>
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* and modifications by Joakim Tjernlund <joakim.tjernlund@lumentis.se>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/bitops.h>
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#include <asm/pgtable.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include "fs_enet.h"
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/*************************************************/
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/*
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* Generic PHY support.
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* Should work for all PHYs, but link change is detected by polling
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*/
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static void generic_timer_callback(unsigned long data)
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{
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struct net_device *dev = (struct net_device *)data;
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struct fs_enet_private *fep = netdev_priv(dev);
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fep->phy_timer_list.expires = jiffies + HZ / 2;
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add_timer(&fep->phy_timer_list);
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fs_mii_link_status_change_check(dev, 0);
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}
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static void generic_startup(struct net_device *dev)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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fep->phy_timer_list.expires = jiffies + HZ / 2; /* every 500ms */
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fep->phy_timer_list.data = (unsigned long)dev;
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fep->phy_timer_list.function = generic_timer_callback;
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add_timer(&fep->phy_timer_list);
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}
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static void generic_shutdown(struct net_device *dev)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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del_timer_sync(&fep->phy_timer_list);
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}
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/* ------------------------------------------------------------------------- */
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/* The Davicom DM9161 is used on the NETTA board */
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/* register definitions */
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#define MII_DM9161_ANAR 4 /* Aux. Config Register */
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#define MII_DM9161_ACR 16 /* Aux. Config Register */
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#define MII_DM9161_ACSR 17 /* Aux. Config/Status Register */
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#define MII_DM9161_10TCSR 18 /* 10BaseT Config/Status Reg. */
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#define MII_DM9161_INTR 21 /* Interrupt Register */
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#define MII_DM9161_RECR 22 /* Receive Error Counter Reg. */
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#define MII_DM9161_DISCR 23 /* Disconnect Counter Register */
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static void dm9161_startup(struct net_device *dev)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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fs_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0000);
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/* Start autonegotiation */
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fs_mii_write(dev, fep->mii_if.phy_id, MII_BMCR, 0x1200);
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set_current_state(TASK_UNINTERRUPTIBLE);
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schedule_timeout(HZ*8);
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}
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static void dm9161_ack_int(struct net_device *dev)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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fs_mii_read(dev, fep->mii_if.phy_id, MII_DM9161_INTR);
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}
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static void dm9161_shutdown(struct net_device *dev)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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fs_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0f00);
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}
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/**********************************************************************************/
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static const struct phy_info phy_info[] = {
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{
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.id = 0x00181b88,
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.name = "DM9161",
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.startup = dm9161_startup,
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.ack_int = dm9161_ack_int,
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.shutdown = dm9161_shutdown,
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}, {
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.id = 0,
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.name = "GENERIC",
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.startup = generic_startup,
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.shutdown = generic_shutdown,
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},
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};
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/**********************************************************************************/
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static int phy_id_detect(struct net_device *dev)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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const struct fs_platform_info *fpi = fep->fpi;
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struct fs_enet_mii_bus *bus = fep->mii_bus;
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int i, r, start, end, phytype, physubtype;
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const struct phy_info *phy;
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int phy_hwid, phy_id;
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phy_hwid = -1;
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fep->phy = NULL;
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/* auto-detect? */
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if (fpi->phy_addr == -1) {
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start = 1;
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end = 32;
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} else { /* direct */
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start = fpi->phy_addr;
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end = start + 1;
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}
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for (phy_id = start; phy_id < end; phy_id++) {
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/* skip already used phy addresses on this bus */
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if (bus->usage_map & (1 << phy_id))
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continue;
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r = fs_mii_read(dev, phy_id, MII_PHYSID1);
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if (r == -1 || (phytype = (r & 0xffff)) == 0xffff)
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continue;
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r = fs_mii_read(dev, phy_id, MII_PHYSID2);
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if (r == -1 || (physubtype = (r & 0xffff)) == 0xffff)
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continue;
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phy_hwid = (phytype << 16) | physubtype;
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if (phy_hwid != -1)
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break;
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}
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if (phy_hwid == -1) {
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printk(KERN_ERR DRV_MODULE_NAME
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": %s No PHY detected! range=0x%02x-0x%02x\n",
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dev->name, start, end);
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return -1;
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}
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for (i = 0, phy = phy_info; i < ARRAY_SIZE(phy_info); i++, phy++)
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if (phy->id == (phy_hwid >> 4) || phy->id == 0)
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break;
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if (i >= ARRAY_SIZE(phy_info)) {
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printk(KERN_ERR DRV_MODULE_NAME
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": %s PHY id 0x%08x is not supported!\n",
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dev->name, phy_hwid);
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return -1;
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}
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fep->phy = phy;
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/* mark this address as used */
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bus->usage_map |= (1 << phy_id);
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printk(KERN_INFO DRV_MODULE_NAME
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": %s Phy @ 0x%x, type %s (0x%08x)%s\n",
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dev->name, phy_id, fep->phy->name, phy_hwid,
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fpi->phy_addr == -1 ? " (auto-detected)" : "");
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return phy_id;
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}
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void fs_mii_startup(struct net_device *dev)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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if (fep->phy->startup)
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(*fep->phy->startup) (dev);
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}
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void fs_mii_shutdown(struct net_device *dev)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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if (fep->phy->shutdown)
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(*fep->phy->shutdown) (dev);
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}
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void fs_mii_ack_int(struct net_device *dev)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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if (fep->phy->ack_int)
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(*fep->phy->ack_int) (dev);
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}
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#define MII_LINK 0x0001
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#define MII_HALF 0x0002
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#define MII_FULL 0x0004
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#define MII_BASE4 0x0008
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#define MII_10M 0x0010
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#define MII_100M 0x0020
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#define MII_1G 0x0040
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#define MII_10G 0x0080
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/* return full mii info at one gulp, with a usable form */
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static unsigned int mii_full_status(struct mii_if_info *mii)
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{
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unsigned int status;
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int bmsr, adv, lpa, neg;
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struct fs_enet_private* fep = netdev_priv(mii->dev);
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/* first, a dummy read, needed to latch some MII phys */
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(void)mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
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bmsr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
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/* no link */
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if ((bmsr & BMSR_LSTATUS) == 0)
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return 0;
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status = MII_LINK;
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/* Lets look what ANEG says if it's supported - otherwize we shall
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take the right values from the platform info*/
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if(!mii->force_media) {
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/* autoneg not completed; don't bother */
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if ((bmsr & BMSR_ANEGCOMPLETE) == 0)
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return 0;
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adv = (*mii->mdio_read)(mii->dev, mii->phy_id, MII_ADVERTISE);
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lpa = (*mii->mdio_read)(mii->dev, mii->phy_id, MII_LPA);
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neg = lpa & adv;
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} else {
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neg = fep->fpi->bus_info->lpa;
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}
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if (neg & LPA_100FULL)
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status |= MII_FULL | MII_100M;
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else if (neg & LPA_100BASE4)
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status |= MII_FULL | MII_BASE4 | MII_100M;
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else if (neg & LPA_100HALF)
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status |= MII_HALF | MII_100M;
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else if (neg & LPA_10FULL)
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status |= MII_FULL | MII_10M;
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else
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status |= MII_HALF | MII_10M;
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return status;
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}
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void fs_mii_link_status_change_check(struct net_device *dev, int init_media)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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struct mii_if_info *mii = &fep->mii_if;
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unsigned int mii_status;
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int ok_to_print, link, duplex, speed;
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unsigned long flags;
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ok_to_print = netif_msg_link(fep);
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mii_status = mii_full_status(mii);
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if (!init_media && mii_status == fep->last_mii_status)
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return;
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fep->last_mii_status = mii_status;
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link = !!(mii_status & MII_LINK);
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duplex = !!(mii_status & MII_FULL);
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speed = (mii_status & MII_100M) ? 100 : 10;
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if (link == 0) {
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netif_carrier_off(mii->dev);
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netif_stop_queue(dev);
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if (!init_media) {
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spin_lock_irqsave(&fep->lock, flags);
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(*fep->ops->stop)(dev);
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spin_unlock_irqrestore(&fep->lock, flags);
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}
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if (ok_to_print)
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printk(KERN_INFO "%s: link down\n", mii->dev->name);
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} else {
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mii->full_duplex = duplex;
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netif_carrier_on(mii->dev);
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spin_lock_irqsave(&fep->lock, flags);
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fep->duplex = duplex;
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fep->speed = speed;
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(*fep->ops->restart)(dev);
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spin_unlock_irqrestore(&fep->lock, flags);
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netif_start_queue(dev);
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if (ok_to_print)
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printk(KERN_INFO "%s: link up, %dMbps, %s-duplex\n",
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dev->name, speed, duplex ? "full" : "half");
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}
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}
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/**********************************************************************************/
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int fs_mii_read(struct net_device *dev, int phy_id, int location)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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struct fs_enet_mii_bus *bus = fep->mii_bus;
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&bus->mii_lock, flags);
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ret = (*bus->mii_read)(bus, phy_id, location);
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spin_unlock_irqrestore(&bus->mii_lock, flags);
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return ret;
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}
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void fs_mii_write(struct net_device *dev, int phy_id, int location, int value)
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{
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struct fs_enet_private *fep = netdev_priv(dev);
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struct fs_enet_mii_bus *bus = fep->mii_bus;
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unsigned long flags;
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spin_lock_irqsave(&bus->mii_lock, flags);
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(*bus->mii_write)(bus, phy_id, location, value);
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spin_unlock_irqrestore(&bus->mii_lock, flags);
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}
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/*****************************************************************************/
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/* list of all registered mii buses */
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static LIST_HEAD(fs_mii_bus_list);
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static struct fs_enet_mii_bus *lookup_bus(int method, int id)
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{
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struct list_head *ptr;
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struct fs_enet_mii_bus *bus;
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list_for_each(ptr, &fs_mii_bus_list) {
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bus = list_entry(ptr, struct fs_enet_mii_bus, list);
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if (bus->bus_info->method == method &&
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bus->bus_info->id == id)
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return bus;
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}
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return NULL;
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}
|
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|
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static struct fs_enet_mii_bus *create_bus(const struct fs_mii_bus_info *bi)
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{
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struct fs_enet_mii_bus *bus;
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int ret = 0;
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bus = kmalloc(sizeof(*bus), GFP_KERNEL);
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if (bus == NULL) {
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ret = -ENOMEM;
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goto err;
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}
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memset(bus, 0, sizeof(*bus));
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spin_lock_init(&bus->mii_lock);
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bus->bus_info = bi;
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bus->refs = 0;
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bus->usage_map = 0;
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/* perform initialization */
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switch (bi->method) {
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case fsmii_fixed:
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ret = fs_mii_fixed_init(bus);
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if (ret != 0)
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goto err;
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break;
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case fsmii_bitbang:
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ret = fs_mii_bitbang_init(bus);
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if (ret != 0)
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goto err;
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break;
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#ifdef CONFIG_FS_ENET_HAS_FEC
|
||||
case fsmii_fec:
|
||||
ret = fs_mii_fec_init(bus);
|
||||
if (ret != 0)
|
||||
goto err;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
list_add(&bus->list, &fs_mii_bus_list);
|
||||
|
||||
return bus;
|
||||
|
||||
err:
|
||||
if (bus)
|
||||
kfree(bus);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
static void destroy_bus(struct fs_enet_mii_bus *bus)
|
||||
{
|
||||
/* remove from bus list */
|
||||
list_del(&bus->list);
|
||||
|
||||
/* nothing more needed */
|
||||
kfree(bus);
|
||||
}
|
||||
|
||||
int fs_mii_connect(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
struct fs_enet_mii_bus *bus = NULL;
|
||||
|
||||
/* check method validity */
|
||||
switch (fpi->bus_info->method) {
|
||||
case fsmii_fixed:
|
||||
case fsmii_bitbang:
|
||||
break;
|
||||
#ifdef CONFIG_FS_ENET_HAS_FEC
|
||||
case fsmii_fec:
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printk(KERN_ERR DRV_MODULE_NAME
|
||||
": %s Unknown MII bus method (%d)!\n",
|
||||
dev->name, fpi->bus_info->method);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
bus = lookup_bus(fpi->bus_info->method, fpi->bus_info->id);
|
||||
|
||||
/* if not found create new bus */
|
||||
if (bus == NULL) {
|
||||
bus = create_bus(fpi->bus_info);
|
||||
if (IS_ERR(bus)) {
|
||||
printk(KERN_ERR DRV_MODULE_NAME
|
||||
": %s MII bus creation failure!\n", dev->name);
|
||||
return PTR_ERR(bus);
|
||||
}
|
||||
}
|
||||
|
||||
bus->refs++;
|
||||
|
||||
fep->mii_bus = bus;
|
||||
|
||||
fep->mii_if.dev = dev;
|
||||
fep->mii_if.phy_id_mask = 0x1f;
|
||||
fep->mii_if.reg_num_mask = 0x1f;
|
||||
fep->mii_if.mdio_read = fs_mii_read;
|
||||
fep->mii_if.mdio_write = fs_mii_write;
|
||||
fep->mii_if.force_media = fpi->bus_info->disable_aneg;
|
||||
fep->mii_if.phy_id = phy_id_detect(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fs_mii_disconnect(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
struct fs_enet_mii_bus *bus = NULL;
|
||||
|
||||
bus = fep->mii_bus;
|
||||
fep->mii_bus = NULL;
|
||||
|
||||
if (--bus->refs <= 0)
|
||||
destroy_bus(bus);
|
||||
}
|
||||
|
|
@ -0,0 +1,245 @@
|
|||
#ifndef FS_ENET_H
|
||||
#define FS_ENET_H
|
||||
|
||||
#include <linux/mii.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#include <linux/fs_enet_pd.h>
|
||||
|
||||
#include <asm/dma-mapping.h>
|
||||
|
||||
#ifdef CONFIG_CPM1
|
||||
#include <asm/commproc.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPM2
|
||||
#include <asm/cpm2.h>
|
||||
#endif
|
||||
|
||||
/* hw driver ops */
|
||||
struct fs_ops {
|
||||
int (*setup_data)(struct net_device *dev);
|
||||
int (*allocate_bd)(struct net_device *dev);
|
||||
void (*free_bd)(struct net_device *dev);
|
||||
void (*cleanup_data)(struct net_device *dev);
|
||||
void (*set_multicast_list)(struct net_device *dev);
|
||||
void (*restart)(struct net_device *dev);
|
||||
void (*stop)(struct net_device *dev);
|
||||
void (*pre_request_irq)(struct net_device *dev, int irq);
|
||||
void (*post_free_irq)(struct net_device *dev, int irq);
|
||||
void (*napi_clear_rx_event)(struct net_device *dev);
|
||||
void (*napi_enable_rx)(struct net_device *dev);
|
||||
void (*napi_disable_rx)(struct net_device *dev);
|
||||
void (*rx_bd_done)(struct net_device *dev);
|
||||
void (*tx_kickstart)(struct net_device *dev);
|
||||
u32 (*get_int_events)(struct net_device *dev);
|
||||
void (*clear_int_events)(struct net_device *dev, u32 int_events);
|
||||
void (*ev_error)(struct net_device *dev, u32 int_events);
|
||||
int (*get_regs)(struct net_device *dev, void *p, int *sizep);
|
||||
int (*get_regs_len)(struct net_device *dev);
|
||||
void (*tx_restart)(struct net_device *dev);
|
||||
};
|
||||
|
||||
struct phy_info {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
void (*startup) (struct net_device * dev);
|
||||
void (*shutdown) (struct net_device * dev);
|
||||
void (*ack_int) (struct net_device * dev);
|
||||
};
|
||||
|
||||
/* The FEC stores dest/src/type, data, and checksum for receive packets.
|
||||
*/
|
||||
#define MAX_MTU 1508 /* Allow fullsized pppoe packets over VLAN */
|
||||
#define MIN_MTU 46 /* this is data size */
|
||||
#define CRC_LEN 4
|
||||
|
||||
#define PKT_MAXBUF_SIZE (MAX_MTU+ETH_HLEN+CRC_LEN)
|
||||
#define PKT_MINBUF_SIZE (MIN_MTU+ETH_HLEN+CRC_LEN)
|
||||
|
||||
/* Must be a multiple of 32 (to cover both FEC & FCC) */
|
||||
#define PKT_MAXBLR_SIZE ((PKT_MAXBUF_SIZE + 31) & ~31)
|
||||
/* This is needed so that invalidate_xxx wont invalidate too much */
|
||||
#define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE)
|
||||
|
||||
struct fs_enet_mii_bus {
|
||||
struct list_head list;
|
||||
spinlock_t mii_lock;
|
||||
const struct fs_mii_bus_info *bus_info;
|
||||
int refs;
|
||||
u32 usage_map;
|
||||
|
||||
int (*mii_read)(struct fs_enet_mii_bus *bus,
|
||||
int phy_id, int location);
|
||||
|
||||
void (*mii_write)(struct fs_enet_mii_bus *bus,
|
||||
int phy_id, int location, int value);
|
||||
|
||||
union {
|
||||
struct {
|
||||
unsigned int mii_speed;
|
||||
void *fecp;
|
||||
} fec;
|
||||
|
||||
struct {
|
||||
/* note that the actual port size may */
|
||||
/* be different; cpm(s) handle it OK */
|
||||
u8 mdio_msk;
|
||||
u8 *mdio_dir;
|
||||
u8 *mdio_dat;
|
||||
u8 mdc_msk;
|
||||
u8 *mdc_dir;
|
||||
u8 *mdc_dat;
|
||||
} bitbang;
|
||||
|
||||
struct {
|
||||
u16 lpa;
|
||||
} fixed;
|
||||
};
|
||||
};
|
||||
|
||||
int fs_mii_bitbang_init(struct fs_enet_mii_bus *bus);
|
||||
int fs_mii_fixed_init(struct fs_enet_mii_bus *bus);
|
||||
int fs_mii_fec_init(struct fs_enet_mii_bus *bus);
|
||||
|
||||
struct fs_enet_private {
|
||||
struct device *dev; /* pointer back to the device (must be initialized first) */
|
||||
spinlock_t lock; /* during all ops except TX pckt processing */
|
||||
spinlock_t tx_lock; /* during fs_start_xmit and fs_tx */
|
||||
const struct fs_platform_info *fpi;
|
||||
const struct fs_ops *ops;
|
||||
int rx_ring, tx_ring;
|
||||
dma_addr_t ring_mem_addr;
|
||||
void *ring_base;
|
||||
struct sk_buff **rx_skbuff;
|
||||
struct sk_buff **tx_skbuff;
|
||||
cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
|
||||
cbd_t *tx_bd_base;
|
||||
cbd_t *dirty_tx; /* ring entries to be free()ed. */
|
||||
cbd_t *cur_rx;
|
||||
cbd_t *cur_tx;
|
||||
int tx_free;
|
||||
struct net_device_stats stats;
|
||||
struct timer_list phy_timer_list;
|
||||
const struct phy_info *phy;
|
||||
u32 msg_enable;
|
||||
struct mii_if_info mii_if;
|
||||
unsigned int last_mii_status;
|
||||
struct fs_enet_mii_bus *mii_bus;
|
||||
int interrupt;
|
||||
|
||||
int duplex, speed; /* current settings */
|
||||
|
||||
/* event masks */
|
||||
u32 ev_napi_rx; /* mask of NAPI rx events */
|
||||
u32 ev_rx; /* rx event mask */
|
||||
u32 ev_tx; /* tx event mask */
|
||||
u32 ev_err; /* error event mask */
|
||||
|
||||
u16 bd_rx_empty; /* mask of BD rx empty */
|
||||
u16 bd_rx_err; /* mask of BD rx errors */
|
||||
|
||||
union {
|
||||
struct {
|
||||
int idx; /* FEC1 = 0, FEC2 = 1 */
|
||||
void *fecp; /* hw registers */
|
||||
u32 hthi, htlo; /* state for multicast */
|
||||
} fec;
|
||||
|
||||
struct {
|
||||
int idx; /* FCC1-3 = 0-2 */
|
||||
void *fccp; /* hw registers */
|
||||
void *ep; /* parameter ram */
|
||||
void *fcccp; /* hw registers cont. */
|
||||
void *mem; /* FCC DPRAM */
|
||||
u32 gaddrh, gaddrl; /* group address */
|
||||
} fcc;
|
||||
|
||||
struct {
|
||||
int idx; /* FEC1 = 0, FEC2 = 1 */
|
||||
void *sccp; /* hw registers */
|
||||
void *ep; /* parameter ram */
|
||||
u32 hthi, htlo; /* state for multicast */
|
||||
} scc;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
int fs_mii_read(struct net_device *dev, int phy_id, int location);
|
||||
void fs_mii_write(struct net_device *dev, int phy_id, int location, int value);
|
||||
|
||||
void fs_mii_startup(struct net_device *dev);
|
||||
void fs_mii_shutdown(struct net_device *dev);
|
||||
void fs_mii_ack_int(struct net_device *dev);
|
||||
|
||||
void fs_mii_link_status_change_check(struct net_device *dev, int init_media);
|
||||
|
||||
void fs_init_bds(struct net_device *dev);
|
||||
void fs_cleanup_bds(struct net_device *dev);
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
#define DRV_MODULE_NAME "fs_enet"
|
||||
#define PFX DRV_MODULE_NAME ": "
|
||||
#define DRV_MODULE_VERSION "1.0"
|
||||
#define DRV_MODULE_RELDATE "Aug 8, 2005"
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
int fs_enet_platform_init(void);
|
||||
void fs_enet_platform_cleanup(void);
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
/* buffer descriptor access macros */
|
||||
|
||||
/* access macros */
|
||||
#if defined(CONFIG_CPM1)
|
||||
/* for a a CPM1 __raw_xxx's are sufficient */
|
||||
#define __cbd_out32(addr, x) __raw_writel(x, addr)
|
||||
#define __cbd_out16(addr, x) __raw_writew(x, addr)
|
||||
#define __cbd_in32(addr) __raw_readl(addr)
|
||||
#define __cbd_in16(addr) __raw_readw(addr)
|
||||
#else
|
||||
/* for others play it safe */
|
||||
#define __cbd_out32(addr, x) out_be32(addr, x)
|
||||
#define __cbd_out16(addr, x) out_be16(addr, x)
|
||||
#define __cbd_in32(addr) in_be32(addr)
|
||||
#define __cbd_in16(addr) in_be16(addr)
|
||||
#endif
|
||||
|
||||
/* write */
|
||||
#define CBDW_SC(_cbd, _sc) __cbd_out16(&(_cbd)->cbd_sc, (_sc))
|
||||
#define CBDW_DATLEN(_cbd, _datlen) __cbd_out16(&(_cbd)->cbd_datlen, (_datlen))
|
||||
#define CBDW_BUFADDR(_cbd, _bufaddr) __cbd_out32(&(_cbd)->cbd_bufaddr, (_bufaddr))
|
||||
|
||||
/* read */
|
||||
#define CBDR_SC(_cbd) __cbd_in16(&(_cbd)->cbd_sc)
|
||||
#define CBDR_DATLEN(_cbd) __cbd_in16(&(_cbd)->cbd_datlen)
|
||||
#define CBDR_BUFADDR(_cbd) __cbd_in32(&(_cbd)->cbd_bufaddr)
|
||||
|
||||
/* set bits */
|
||||
#define CBDS_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc))
|
||||
|
||||
/* clear bits */
|
||||
#define CBDC_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc))
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
extern const struct fs_ops fs_fec_ops;
|
||||
extern const struct fs_ops fs_fcc_ops;
|
||||
extern const struct fs_ops fs_scc_ops;
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
/* handy pointer to the immap */
|
||||
extern void *fs_enet_immap;
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,578 @@
|
|||
/*
|
||||
* FCC driver for Motorola MPC82xx (PQ2).
|
||||
*
|
||||
* Copyright (c) 2003 Intracom S.A.
|
||||
* by Pantelis Antoniou <panto@intracom.gr>
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc.
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/fs.h>
|
||||
|
||||
#include <asm/immap_cpm2.h>
|
||||
#include <asm/mpc8260.h>
|
||||
#include <asm/cpm2.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
#include "fs_enet.h"
|
||||
|
||||
/*************************************************/
|
||||
|
||||
/* FCC access macros */
|
||||
|
||||
#define __fcc_out32(addr, x) out_be32((unsigned *)addr, x)
|
||||
#define __fcc_out16(addr, x) out_be16((unsigned short *)addr, x)
|
||||
#define __fcc_out8(addr, x) out_8((unsigned char *)addr, x)
|
||||
#define __fcc_in32(addr) in_be32((unsigned *)addr)
|
||||
#define __fcc_in16(addr) in_be16((unsigned short *)addr)
|
||||
#define __fcc_in8(addr) in_8((unsigned char *)addr)
|
||||
|
||||
/* parameter space */
|
||||
|
||||
/* write, read, set bits, clear bits */
|
||||
#define W32(_p, _m, _v) __fcc_out32(&(_p)->_m, (_v))
|
||||
#define R32(_p, _m) __fcc_in32(&(_p)->_m)
|
||||
#define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v))
|
||||
#define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v))
|
||||
|
||||
#define W16(_p, _m, _v) __fcc_out16(&(_p)->_m, (_v))
|
||||
#define R16(_p, _m) __fcc_in16(&(_p)->_m)
|
||||
#define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v))
|
||||
#define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v))
|
||||
|
||||
#define W8(_p, _m, _v) __fcc_out8(&(_p)->_m, (_v))
|
||||
#define R8(_p, _m) __fcc_in8(&(_p)->_m)
|
||||
#define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v))
|
||||
#define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v))
|
||||
|
||||
/*************************************************/
|
||||
|
||||
#define FCC_MAX_MULTICAST_ADDRS 64
|
||||
|
||||
#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
|
||||
#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
#define mk_mii_end 0
|
||||
|
||||
#define MAX_CR_CMD_LOOPS 10000
|
||||
|
||||
static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 mcn, u32 op)
|
||||
{
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
|
||||
cpm2_map_t *immap = fs_enet_immap;
|
||||
cpm_cpm2_t *cpmp = &immap->im_cpm;
|
||||
u32 v;
|
||||
int i;
|
||||
|
||||
/* Currently I don't know what feature call will look like. But
|
||||
I guess there'd be something like do_cpm_cmd() which will require page & sblock */
|
||||
v = mk_cr_cmd(fpi->cp_page, fpi->cp_block, mcn, op);
|
||||
W32(cpmp, cp_cpcr, v | CPM_CR_FLG);
|
||||
for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
|
||||
if ((R32(cpmp, cp_cpcr) & CPM_CR_FLG) == 0)
|
||||
break;
|
||||
|
||||
if (i >= MAX_CR_CMD_LOOPS) {
|
||||
printk(KERN_ERR "%s(): Not able to issue CPM command\n",
|
||||
__FUNCTION__);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_pd_setup(struct fs_enet_private *fep)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(fep->dev);
|
||||
struct resource *r;
|
||||
|
||||
/* Fill out IRQ field */
|
||||
fep->interrupt = platform_get_irq(pdev, 0);
|
||||
|
||||
/* Attach the memory for the FCC Parameter RAM */
|
||||
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_pram");
|
||||
fep->fcc.ep = (void *)r->start;
|
||||
|
||||
if (fep->fcc.ep == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_regs");
|
||||
fep->fcc.fccp = (void *)r->start;
|
||||
|
||||
if (fep->fcc.fccp == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
fep->fcc.fcccp = (void *)fep->fpi->fcc_regs_c;
|
||||
|
||||
if (fep->fcc.fcccp == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB)
|
||||
#define FCC_RX_EVENT (FCC_ENET_RXF)
|
||||
#define FCC_TX_EVENT (FCC_ENET_TXB)
|
||||
#define FCC_ERR_EVENT_MSK (FCC_ENET_TXE | FCC_ENET_BSY)
|
||||
|
||||
static int setup_data(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
|
||||
fep->fcc.idx = fs_get_fcc_index(fpi->fs_no);
|
||||
if ((unsigned int)fep->fcc.idx >= 3) /* max 3 FCCs */
|
||||
return -EINVAL;
|
||||
|
||||
fep->fcc.mem = (void *)fpi->mem_offset;
|
||||
|
||||
if (do_pd_setup(fep) != 0)
|
||||
return -EINVAL;
|
||||
|
||||
fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK;
|
||||
fep->ev_rx = FCC_RX_EVENT;
|
||||
fep->ev_tx = FCC_TX_EVENT;
|
||||
fep->ev_err = FCC_ERR_EVENT_MSK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int allocate_bd(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
|
||||
fep->ring_base = dma_alloc_coherent(fep->dev,
|
||||
(fpi->tx_ring + fpi->rx_ring) *
|
||||
sizeof(cbd_t), &fep->ring_mem_addr,
|
||||
GFP_KERNEL);
|
||||
if (fep->ring_base == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void free_bd(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
|
||||
if (fep->ring_base)
|
||||
dma_free_coherent(fep->dev,
|
||||
(fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
|
||||
fep->ring_base, fep->ring_mem_addr);
|
||||
}
|
||||
|
||||
static void cleanup_data(struct net_device *dev)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
static void set_promiscuous_mode(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fcc_t *fccp = fep->fcc.fccp;
|
||||
|
||||
S32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
|
||||
}
|
||||
|
||||
static void set_multicast_start(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fcc_enet_t *ep = fep->fcc.ep;
|
||||
|
||||
W32(ep, fen_gaddrh, 0);
|
||||
W32(ep, fen_gaddrl, 0);
|
||||
}
|
||||
|
||||
static void set_multicast_one(struct net_device *dev, const u8 *mac)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fcc_enet_t *ep = fep->fcc.ep;
|
||||
u16 taddrh, taddrm, taddrl;
|
||||
|
||||
taddrh = ((u16)mac[5] << 8) | mac[4];
|
||||
taddrm = ((u16)mac[3] << 8) | mac[2];
|
||||
taddrl = ((u16)mac[1] << 8) | mac[0];
|
||||
|
||||
W16(ep, fen_taddrh, taddrh);
|
||||
W16(ep, fen_taddrm, taddrm);
|
||||
W16(ep, fen_taddrl, taddrl);
|
||||
fcc_cr_cmd(fep, 0x0C, CPM_CR_SET_GADDR);
|
||||
}
|
||||
|
||||
static void set_multicast_finish(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fcc_t *fccp = fep->fcc.fccp;
|
||||
fcc_enet_t *ep = fep->fcc.ep;
|
||||
|
||||
/* clear promiscuous always */
|
||||
C32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
|
||||
|
||||
/* if all multi or too many multicasts; just enable all */
|
||||
if ((dev->flags & IFF_ALLMULTI) != 0 ||
|
||||
dev->mc_count > FCC_MAX_MULTICAST_ADDRS) {
|
||||
|
||||
W32(ep, fen_gaddrh, 0xffffffff);
|
||||
W32(ep, fen_gaddrl, 0xffffffff);
|
||||
}
|
||||
|
||||
/* read back */
|
||||
fep->fcc.gaddrh = R32(ep, fen_gaddrh);
|
||||
fep->fcc.gaddrl = R32(ep, fen_gaddrl);
|
||||
}
|
||||
|
||||
static void set_multicast_list(struct net_device *dev)
|
||||
{
|
||||
struct dev_mc_list *pmc;
|
||||
|
||||
if ((dev->flags & IFF_PROMISC) == 0) {
|
||||
set_multicast_start(dev);
|
||||
for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
|
||||
set_multicast_one(dev, pmc->dmi_addr);
|
||||
set_multicast_finish(dev);
|
||||
} else
|
||||
set_promiscuous_mode(dev);
|
||||
}
|
||||
|
||||
static void restart(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
fcc_t *fccp = fep->fcc.fccp;
|
||||
fcc_c_t *fcccp = fep->fcc.fcccp;
|
||||
fcc_enet_t *ep = fep->fcc.ep;
|
||||
dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
|
||||
u16 paddrh, paddrm, paddrl;
|
||||
u16 mem_addr;
|
||||
const unsigned char *mac;
|
||||
int i;
|
||||
|
||||
C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
|
||||
|
||||
/* clear everything (slow & steady does it) */
|
||||
for (i = 0; i < sizeof(*ep); i++)
|
||||
__fcc_out8((char *)ep + i, 0);
|
||||
|
||||
/* get physical address */
|
||||
rx_bd_base_phys = fep->ring_mem_addr;
|
||||
tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
|
||||
|
||||
/* point to bds */
|
||||
W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
|
||||
W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);
|
||||
|
||||
/* Set maximum bytes per receive buffer.
|
||||
* It must be a multiple of 32.
|
||||
*/
|
||||
W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);
|
||||
|
||||
W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
|
||||
W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
|
||||
|
||||
/* Allocate space in the reserved FCC area of DPRAM for the
|
||||
* internal buffers. No one uses this space (yet), so we
|
||||
* can do this. Later, we will add resource management for
|
||||
* this area.
|
||||
*/
|
||||
|
||||
mem_addr = (u32) fep->fcc.mem; /* de-fixup dpram offset */
|
||||
|
||||
W16(ep, fen_genfcc.fcc_riptr, (mem_addr & 0xffff));
|
||||
W16(ep, fen_genfcc.fcc_tiptr, ((mem_addr + 32) & 0xffff));
|
||||
W16(ep, fen_padptr, mem_addr + 64);
|
||||
|
||||
/* fill with special symbol... */
|
||||
memset(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);
|
||||
|
||||
W32(ep, fen_genfcc.fcc_rbptr, 0);
|
||||
W32(ep, fen_genfcc.fcc_tbptr, 0);
|
||||
W32(ep, fen_genfcc.fcc_rcrc, 0);
|
||||
W32(ep, fen_genfcc.fcc_tcrc, 0);
|
||||
W16(ep, fen_genfcc.fcc_res1, 0);
|
||||
W32(ep, fen_genfcc.fcc_res2, 0);
|
||||
|
||||
/* no CAM */
|
||||
W32(ep, fen_camptr, 0);
|
||||
|
||||
/* Set CRC preset and mask */
|
||||
W32(ep, fen_cmask, 0xdebb20e3);
|
||||
W32(ep, fen_cpres, 0xffffffff);
|
||||
|
||||
W32(ep, fen_crcec, 0); /* CRC Error counter */
|
||||
W32(ep, fen_alec, 0); /* alignment error counter */
|
||||
W32(ep, fen_disfc, 0); /* discard frame counter */
|
||||
W16(ep, fen_retlim, 15); /* Retry limit threshold */
|
||||
W16(ep, fen_pper, 0); /* Normal persistence */
|
||||
|
||||
/* set group address */
|
||||
W32(ep, fen_gaddrh, fep->fcc.gaddrh);
|
||||
W32(ep, fen_gaddrl, fep->fcc.gaddrh);
|
||||
|
||||
/* Clear hash filter tables */
|
||||
W32(ep, fen_iaddrh, 0);
|
||||
W32(ep, fen_iaddrl, 0);
|
||||
|
||||
/* Clear the Out-of-sequence TxBD */
|
||||
W16(ep, fen_tfcstat, 0);
|
||||
W16(ep, fen_tfclen, 0);
|
||||
W32(ep, fen_tfcptr, 0);
|
||||
|
||||
W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */
|
||||
W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */
|
||||
|
||||
/* set address */
|
||||
mac = dev->dev_addr;
|
||||
paddrh = ((u16)mac[5] << 8) | mac[4];
|
||||
paddrm = ((u16)mac[3] << 8) | mac[2];
|
||||
paddrl = ((u16)mac[1] << 8) | mac[0];
|
||||
|
||||
W16(ep, fen_paddrh, paddrh);
|
||||
W16(ep, fen_paddrm, paddrm);
|
||||
W16(ep, fen_paddrl, paddrl);
|
||||
|
||||
W16(ep, fen_taddrh, 0);
|
||||
W16(ep, fen_taddrm, 0);
|
||||
W16(ep, fen_taddrl, 0);
|
||||
|
||||
W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */
|
||||
W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */
|
||||
|
||||
/* Clear stat counters, in case we ever enable RMON */
|
||||
W32(ep, fen_octc, 0);
|
||||
W32(ep, fen_colc, 0);
|
||||
W32(ep, fen_broc, 0);
|
||||
W32(ep, fen_mulc, 0);
|
||||
W32(ep, fen_uspc, 0);
|
||||
W32(ep, fen_frgc, 0);
|
||||
W32(ep, fen_ospc, 0);
|
||||
W32(ep, fen_jbrc, 0);
|
||||
W32(ep, fen_p64c, 0);
|
||||
W32(ep, fen_p65c, 0);
|
||||
W32(ep, fen_p128c, 0);
|
||||
W32(ep, fen_p256c, 0);
|
||||
W32(ep, fen_p512c, 0);
|
||||
W32(ep, fen_p1024c, 0);
|
||||
|
||||
W16(ep, fen_rfthr, 0); /* Suggested by manual */
|
||||
W16(ep, fen_rfcnt, 0);
|
||||
W16(ep, fen_cftype, 0);
|
||||
|
||||
fs_init_bds(dev);
|
||||
|
||||
/* adjust to speed (for RMII mode) */
|
||||
if (fpi->use_rmii) {
|
||||
if (fep->speed == 100)
|
||||
C8(fcccp, fcc_gfemr, 0x20);
|
||||
else
|
||||
S8(fcccp, fcc_gfemr, 0x20);
|
||||
}
|
||||
|
||||
fcc_cr_cmd(fep, 0x0c, CPM_CR_INIT_TRX);
|
||||
|
||||
/* clear events */
|
||||
W16(fccp, fcc_fcce, 0xffff);
|
||||
|
||||
/* Enable interrupts we wish to service */
|
||||
W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
|
||||
|
||||
/* Set GFMR to enable Ethernet operating mode */
|
||||
W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
|
||||
|
||||
/* set sync/delimiters */
|
||||
W16(fccp, fcc_fdsr, 0xd555);
|
||||
|
||||
W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC);
|
||||
|
||||
if (fpi->use_rmii)
|
||||
S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);
|
||||
|
||||
/* adjust to duplex mode */
|
||||
if (fep->duplex)
|
||||
S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
|
||||
else
|
||||
C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
|
||||
|
||||
S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
|
||||
}
|
||||
|
||||
static void stop(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fcc_t *fccp = fep->fcc.fccp;
|
||||
|
||||
/* stop ethernet */
|
||||
C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
|
||||
|
||||
/* clear events */
|
||||
W16(fccp, fcc_fcce, 0xffff);
|
||||
|
||||
/* clear interrupt mask */
|
||||
W16(fccp, fcc_fccm, 0);
|
||||
|
||||
fs_cleanup_bds(dev);
|
||||
}
|
||||
|
||||
static void pre_request_irq(struct net_device *dev, int irq)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
static void post_free_irq(struct net_device *dev, int irq)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
static void napi_clear_rx_event(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fcc_t *fccp = fep->fcc.fccp;
|
||||
|
||||
W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK);
|
||||
}
|
||||
|
||||
static void napi_enable_rx(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fcc_t *fccp = fep->fcc.fccp;
|
||||
|
||||
S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
|
||||
}
|
||||
|
||||
static void napi_disable_rx(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fcc_t *fccp = fep->fcc.fccp;
|
||||
|
||||
C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
|
||||
}
|
||||
|
||||
static void rx_bd_done(struct net_device *dev)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
static void tx_kickstart(struct net_device *dev)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
static u32 get_int_events(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fcc_t *fccp = fep->fcc.fccp;
|
||||
|
||||
return (u32)R16(fccp, fcc_fcce);
|
||||
}
|
||||
|
||||
static void clear_int_events(struct net_device *dev, u32 int_events)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fcc_t *fccp = fep->fcc.fccp;
|
||||
|
||||
W16(fccp, fcc_fcce, int_events & 0xffff);
|
||||
}
|
||||
|
||||
static void ev_error(struct net_device *dev, u32 int_events)
|
||||
{
|
||||
printk(KERN_WARNING DRV_MODULE_NAME
|
||||
": %s FS_ENET ERROR(s) 0x%x\n", dev->name, int_events);
|
||||
}
|
||||
|
||||
int get_regs(struct net_device *dev, void *p, int *sizep)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
|
||||
if (*sizep < sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t))
|
||||
return -EINVAL;
|
||||
|
||||
memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t));
|
||||
p = (char *)p + sizeof(fcc_t);
|
||||
|
||||
memcpy_fromio(p, fep->fcc.fcccp, sizeof(fcc_c_t));
|
||||
p = (char *)p + sizeof(fcc_c_t);
|
||||
|
||||
memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int get_regs_len(struct net_device *dev)
|
||||
{
|
||||
return sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t);
|
||||
}
|
||||
|
||||
/* Some transmit errors cause the transmitter to shut
|
||||
* down. We now issue a restart transmit. Since the
|
||||
* errors close the BD and update the pointers, the restart
|
||||
* _should_ pick up without having to reset any of our
|
||||
* pointers either. Also, To workaround 8260 device erratum
|
||||
* CPM37, we must disable and then re-enable the transmitter
|
||||
* following a Late Collision, Underrun, or Retry Limit error.
|
||||
*/
|
||||
void tx_restart(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fcc_t *fccp = fep->fcc.fccp;
|
||||
|
||||
C32(fccp, fcc_gfmr, FCC_GFMR_ENT);
|
||||
udelay(10);
|
||||
S32(fccp, fcc_gfmr, FCC_GFMR_ENT);
|
||||
|
||||
fcc_cr_cmd(fep, 0x0C, CPM_CR_RESTART_TX);
|
||||
}
|
||||
|
||||
/*************************************************************************/
|
||||
|
||||
const struct fs_ops fs_fcc_ops = {
|
||||
.setup_data = setup_data,
|
||||
.cleanup_data = cleanup_data,
|
||||
.set_multicast_list = set_multicast_list,
|
||||
.restart = restart,
|
||||
.stop = stop,
|
||||
.pre_request_irq = pre_request_irq,
|
||||
.post_free_irq = post_free_irq,
|
||||
.napi_clear_rx_event = napi_clear_rx_event,
|
||||
.napi_enable_rx = napi_enable_rx,
|
||||
.napi_disable_rx = napi_disable_rx,
|
||||
.rx_bd_done = rx_bd_done,
|
||||
.tx_kickstart = tx_kickstart,
|
||||
.get_int_events = get_int_events,
|
||||
.clear_int_events = clear_int_events,
|
||||
.ev_error = ev_error,
|
||||
.get_regs = get_regs,
|
||||
.get_regs_len = get_regs_len,
|
||||
.tx_restart = tx_restart,
|
||||
.allocate_bd = allocate_bd,
|
||||
.free_bd = free_bd,
|
||||
};
|
||||
|
|
@ -0,0 +1,653 @@
|
|||
/*
|
||||
* Freescale Ethernet controllers
|
||||
*
|
||||
* Copyright (c) 2005 Intracom S.A.
|
||||
* by Pantelis Antoniou <panto@intracom.gr>
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc.
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/fs.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
#ifdef CONFIG_8xx
|
||||
#include <asm/8xx_immap.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mpc8xx.h>
|
||||
#include <asm/commproc.h>
|
||||
#endif
|
||||
|
||||
#include "fs_enet.h"
|
||||
|
||||
/*************************************************/
|
||||
|
||||
#if defined(CONFIG_CPM1)
|
||||
/* for a CPM1 __raw_xxx's are sufficient */
|
||||
#define __fs_out32(addr, x) __raw_writel(x, addr)
|
||||
#define __fs_out16(addr, x) __raw_writew(x, addr)
|
||||
#define __fs_in32(addr) __raw_readl(addr)
|
||||
#define __fs_in16(addr) __raw_readw(addr)
|
||||
#else
|
||||
/* for others play it safe */
|
||||
#define __fs_out32(addr, x) out_be32(addr, x)
|
||||
#define __fs_out16(addr, x) out_be16(addr, x)
|
||||
#define __fs_in32(addr) in_be32(addr)
|
||||
#define __fs_in16(addr) in_be16(addr)
|
||||
#endif
|
||||
|
||||
/* write */
|
||||
#define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))
|
||||
|
||||
/* read */
|
||||
#define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg)
|
||||
|
||||
/* set bits */
|
||||
#define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
|
||||
|
||||
/* clear bits */
|
||||
#define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
|
||||
|
||||
|
||||
/* CRC polynomium used by the FEC for the multicast group filtering */
|
||||
#define FEC_CRC_POLY 0x04C11DB7
|
||||
|
||||
#define FEC_MAX_MULTICAST_ADDRS 64
|
||||
|
||||
/* Interrupt events/masks.
|
||||
*/
|
||||
#define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */
|
||||
#define FEC_ENET_BABR 0x40000000U /* Babbling receiver */
|
||||
#define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */
|
||||
#define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */
|
||||
#define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */
|
||||
#define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */
|
||||
#define FEC_ENET_RXF 0x02000000U /* Full frame received */
|
||||
#define FEC_ENET_RXB 0x01000000U /* A buffer was received */
|
||||
#define FEC_ENET_MII 0x00800000U /* MII interrupt */
|
||||
#define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */
|
||||
|
||||
#define FEC_ECNTRL_PINMUX 0x00000004
|
||||
#define FEC_ECNTRL_ETHER_EN 0x00000002
|
||||
#define FEC_ECNTRL_RESET 0x00000001
|
||||
|
||||
#define FEC_RCNTRL_BC_REJ 0x00000010
|
||||
#define FEC_RCNTRL_PROM 0x00000008
|
||||
#define FEC_RCNTRL_MII_MODE 0x00000004
|
||||
#define FEC_RCNTRL_DRT 0x00000002
|
||||
#define FEC_RCNTRL_LOOP 0x00000001
|
||||
|
||||
#define FEC_TCNTRL_FDEN 0x00000004
|
||||
#define FEC_TCNTRL_HBC 0x00000002
|
||||
#define FEC_TCNTRL_GTS 0x00000001
|
||||
|
||||
|
||||
/* Make MII read/write commands for the FEC.
|
||||
*/
|
||||
#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
|
||||
#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
#define mk_mii_end 0
|
||||
|
||||
#define FEC_MII_LOOPS 10000
|
||||
|
||||
/*
|
||||
* Delay to wait for FEC reset command to complete (in us)
|
||||
*/
|
||||
#define FEC_RESET_DELAY 50
|
||||
|
||||
static int whack_reset(fec_t * fecp)
|
||||
{
|
||||
int i;
|
||||
|
||||
FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
|
||||
for (i = 0; i < FEC_RESET_DELAY; i++) {
|
||||
if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0)
|
||||
return 0; /* OK */
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int do_pd_setup(struct fs_enet_private *fep)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(fep->dev);
|
||||
struct resource *r;
|
||||
|
||||
/* Fill out IRQ field */
|
||||
fep->interrupt = platform_get_irq_byname(pdev,"interrupt");
|
||||
|
||||
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
|
||||
fep->fec.fecp =(void*)r->start;
|
||||
|
||||
if(fep->fec.fecp == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
#define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF | FEC_ENET_RXB)
|
||||
#define FEC_RX_EVENT (FEC_ENET_RXF)
|
||||
#define FEC_TX_EVENT (FEC_ENET_TXF)
|
||||
#define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR | FEC_ENET_BABR | \
|
||||
FEC_ENET_BABT | FEC_ENET_EBERR)
|
||||
|
||||
static int setup_data(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
|
||||
if (do_pd_setup(fep) != 0)
|
||||
return -EINVAL;
|
||||
|
||||
fep->fec.hthi = 0;
|
||||
fep->fec.htlo = 0;
|
||||
|
||||
fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK;
|
||||
fep->ev_rx = FEC_RX_EVENT;
|
||||
fep->ev_tx = FEC_TX_EVENT;
|
||||
fep->ev_err = FEC_ERR_EVENT_MSK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int allocate_bd(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
|
||||
fep->ring_base = dma_alloc_coherent(fep->dev,
|
||||
(fpi->tx_ring + fpi->rx_ring) *
|
||||
sizeof(cbd_t), &fep->ring_mem_addr,
|
||||
GFP_KERNEL);
|
||||
if (fep->ring_base == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void free_bd(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
|
||||
if(fep->ring_base)
|
||||
dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring)
|
||||
* sizeof(cbd_t),
|
||||
fep->ring_base,
|
||||
fep->ring_mem_addr);
|
||||
}
|
||||
|
||||
static void cleanup_data(struct net_device *dev)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
static void set_promiscuous_mode(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fec_t *fecp = fep->fec.fecp;
|
||||
|
||||
FS(fecp, r_cntrl, FEC_RCNTRL_PROM);
|
||||
}
|
||||
|
||||
static void set_multicast_start(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
|
||||
fep->fec.hthi = 0;
|
||||
fep->fec.htlo = 0;
|
||||
}
|
||||
|
||||
static void set_multicast_one(struct net_device *dev, const u8 *mac)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
int temp, hash_index, i, j;
|
||||
u32 crc, csrVal;
|
||||
u8 byte, msb;
|
||||
|
||||
crc = 0xffffffff;
|
||||
for (i = 0; i < 6; i++) {
|
||||
byte = mac[i];
|
||||
for (j = 0; j < 8; j++) {
|
||||
msb = crc >> 31;
|
||||
crc <<= 1;
|
||||
if (msb ^ (byte & 0x1))
|
||||
crc ^= FEC_CRC_POLY;
|
||||
byte >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
temp = (crc & 0x3f) >> 1;
|
||||
hash_index = ((temp & 0x01) << 4) |
|
||||
((temp & 0x02) << 2) |
|
||||
((temp & 0x04)) |
|
||||
((temp & 0x08) >> 2) |
|
||||
((temp & 0x10) >> 4);
|
||||
csrVal = 1 << hash_index;
|
||||
if (crc & 1)
|
||||
fep->fec.hthi |= csrVal;
|
||||
else
|
||||
fep->fec.htlo |= csrVal;
|
||||
}
|
||||
|
||||
static void set_multicast_finish(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fec_t *fecp = fep->fec.fecp;
|
||||
|
||||
/* if all multi or too many multicasts; just enable all */
|
||||
if ((dev->flags & IFF_ALLMULTI) != 0 ||
|
||||
dev->mc_count > FEC_MAX_MULTICAST_ADDRS) {
|
||||
fep->fec.hthi = 0xffffffffU;
|
||||
fep->fec.htlo = 0xffffffffU;
|
||||
}
|
||||
|
||||
FC(fecp, r_cntrl, FEC_RCNTRL_PROM);
|
||||
FW(fecp, hash_table_high, fep->fec.hthi);
|
||||
FW(fecp, hash_table_low, fep->fec.htlo);
|
||||
}
|
||||
|
||||
static void set_multicast_list(struct net_device *dev)
|
||||
{
|
||||
struct dev_mc_list *pmc;
|
||||
|
||||
if ((dev->flags & IFF_PROMISC) == 0) {
|
||||
set_multicast_start(dev);
|
||||
for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
|
||||
set_multicast_one(dev, pmc->dmi_addr);
|
||||
set_multicast_finish(dev);
|
||||
} else
|
||||
set_promiscuous_mode(dev);
|
||||
}
|
||||
|
||||
static void restart(struct net_device *dev)
|
||||
{
|
||||
#ifdef CONFIG_DUET
|
||||
immap_t *immap = fs_enet_immap;
|
||||
u32 cptr;
|
||||
#endif
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fec_t *fecp = fep->fec.fecp;
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
|
||||
int r;
|
||||
u32 addrhi, addrlo;
|
||||
|
||||
r = whack_reset(fep->fec.fecp);
|
||||
if (r != 0)
|
||||
printk(KERN_ERR DRV_MODULE_NAME
|
||||
": %s FEC Reset FAILED!\n", dev->name);
|
||||
|
||||
/*
|
||||
* Set station address.
|
||||
*/
|
||||
addrhi = ((u32) dev->dev_addr[0] << 24) |
|
||||
((u32) dev->dev_addr[1] << 16) |
|
||||
((u32) dev->dev_addr[2] << 8) |
|
||||
(u32) dev->dev_addr[3];
|
||||
addrlo = ((u32) dev->dev_addr[4] << 24) |
|
||||
((u32) dev->dev_addr[5] << 16);
|
||||
FW(fecp, addr_low, addrhi);
|
||||
FW(fecp, addr_high, addrlo);
|
||||
|
||||
/*
|
||||
* Reset all multicast.
|
||||
*/
|
||||
FW(fecp, hash_table_high, fep->fec.hthi);
|
||||
FW(fecp, hash_table_low, fep->fec.htlo);
|
||||
|
||||
/*
|
||||
* Set maximum receive buffer size.
|
||||
*/
|
||||
FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
|
||||
FW(fecp, r_hash, PKT_MAXBUF_SIZE);
|
||||
|
||||
/* get physical address */
|
||||
rx_bd_base_phys = fep->ring_mem_addr;
|
||||
tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
|
||||
|
||||
/*
|
||||
* Set receive and transmit descriptor base.
|
||||
*/
|
||||
FW(fecp, r_des_start, rx_bd_base_phys);
|
||||
FW(fecp, x_des_start, tx_bd_base_phys);
|
||||
|
||||
fs_init_bds(dev);
|
||||
|
||||
/*
|
||||
* Enable big endian and don't care about SDMA FC.
|
||||
*/
|
||||
FW(fecp, fun_code, 0x78000000);
|
||||
|
||||
/*
|
||||
* Set MII speed.
|
||||
*/
|
||||
FW(fecp, mii_speed, fep->mii_bus->fec.mii_speed);
|
||||
|
||||
/*
|
||||
* Clear any outstanding interrupt.
|
||||
*/
|
||||
FW(fecp, ievent, 0xffc0);
|
||||
FW(fecp, ivec, (fep->interrupt / 2) << 29);
|
||||
|
||||
|
||||
/*
|
||||
* adjust to speed (only for DUET & RMII)
|
||||
*/
|
||||
#ifdef CONFIG_DUET
|
||||
if (fpi->use_rmii) {
|
||||
cptr = in_be32(&immap->im_cpm.cp_cptr);
|
||||
switch (fs_get_fec_index(fpi->fs_no)) {
|
||||
case 0:
|
||||
cptr |= 0x100;
|
||||
if (fep->speed == 10)
|
||||
cptr |= 0x0000010;
|
||||
else if (fep->speed == 100)
|
||||
cptr &= ~0x0000010;
|
||||
break;
|
||||
case 1:
|
||||
cptr |= 0x80;
|
||||
if (fep->speed == 10)
|
||||
cptr |= 0x0000008;
|
||||
else if (fep->speed == 100)
|
||||
cptr &= ~0x0000008;
|
||||
break;
|
||||
default:
|
||||
BUG(); /* should never happen */
|
||||
break;
|
||||
}
|
||||
out_be32(&immap->im_cpm.cp_cptr, cptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
|
||||
/*
|
||||
* adjust to duplex mode
|
||||
*/
|
||||
if (fep->duplex) {
|
||||
FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
|
||||
FS(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
|
||||
} else {
|
||||
FS(fecp, r_cntrl, FEC_RCNTRL_DRT);
|
||||
FC(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable interrupts we wish to service.
|
||||
*/
|
||||
FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |
|
||||
FEC_ENET_RXF | FEC_ENET_RXB);
|
||||
|
||||
/*
|
||||
* And last, enable the transmit and receive processing.
|
||||
*/
|
||||
FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
|
||||
FW(fecp, r_des_active, 0x01000000);
|
||||
}
|
||||
|
||||
static void stop(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fec_t *fecp = fep->fec.fecp;
|
||||
struct fs_enet_mii_bus *bus = fep->mii_bus;
|
||||
const struct fs_mii_bus_info *bi = bus->bus_info;
|
||||
int i;
|
||||
|
||||
if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
|
||||
return; /* already down */
|
||||
|
||||
FW(fecp, x_cntrl, 0x01); /* Graceful transmit stop */
|
||||
for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) &&
|
||||
i < FEC_RESET_DELAY; i++)
|
||||
udelay(1);
|
||||
|
||||
if (i == FEC_RESET_DELAY)
|
||||
printk(KERN_WARNING DRV_MODULE_NAME
|
||||
": %s FEC timeout on graceful transmit stop\n",
|
||||
dev->name);
|
||||
/*
|
||||
* Disable FEC. Let only MII interrupts.
|
||||
*/
|
||||
FW(fecp, imask, 0);
|
||||
FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN);
|
||||
|
||||
fs_cleanup_bds(dev);
|
||||
|
||||
/* shut down FEC1? that's where the mii bus is */
|
||||
if (fep->fec.idx == 0 && bus->refs > 1 && bi->method == fsmii_fec) {
|
||||
FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
|
||||
FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
|
||||
FW(fecp, ievent, FEC_ENET_MII);
|
||||
FW(fecp, mii_speed, bus->fec.mii_speed);
|
||||
}
|
||||
}
|
||||
|
||||
static void pre_request_irq(struct net_device *dev, int irq)
|
||||
{
|
||||
immap_t *immap = fs_enet_immap;
|
||||
u32 siel;
|
||||
|
||||
/* SIU interrupt */
|
||||
if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {
|
||||
|
||||
siel = in_be32(&immap->im_siu_conf.sc_siel);
|
||||
if ((irq & 1) == 0)
|
||||
siel |= (0x80000000 >> irq);
|
||||
else
|
||||
siel &= ~(0x80000000 >> (irq & ~1));
|
||||
out_be32(&immap->im_siu_conf.sc_siel, siel);
|
||||
}
|
||||
}
|
||||
|
||||
static void post_free_irq(struct net_device *dev, int irq)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
static void napi_clear_rx_event(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fec_t *fecp = fep->fec.fecp;
|
||||
|
||||
FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);
|
||||
}
|
||||
|
||||
static void napi_enable_rx(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fec_t *fecp = fep->fec.fecp;
|
||||
|
||||
FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
|
||||
}
|
||||
|
||||
static void napi_disable_rx(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fec_t *fecp = fep->fec.fecp;
|
||||
|
||||
FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
|
||||
}
|
||||
|
||||
static void rx_bd_done(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fec_t *fecp = fep->fec.fecp;
|
||||
|
||||
FW(fecp, r_des_active, 0x01000000);
|
||||
}
|
||||
|
||||
static void tx_kickstart(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fec_t *fecp = fep->fec.fecp;
|
||||
|
||||
FW(fecp, x_des_active, 0x01000000);
|
||||
}
|
||||
|
||||
static u32 get_int_events(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fec_t *fecp = fep->fec.fecp;
|
||||
|
||||
return FR(fecp, ievent) & FR(fecp, imask);
|
||||
}
|
||||
|
||||
static void clear_int_events(struct net_device *dev, u32 int_events)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
fec_t *fecp = fep->fec.fecp;
|
||||
|
||||
FW(fecp, ievent, int_events);
|
||||
}
|
||||
|
||||
static void ev_error(struct net_device *dev, u32 int_events)
|
||||
{
|
||||
printk(KERN_WARNING DRV_MODULE_NAME
|
||||
": %s FEC ERROR(s) 0x%x\n", dev->name, int_events);
|
||||
}
|
||||
|
||||
int get_regs(struct net_device *dev, void *p, int *sizep)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
|
||||
if (*sizep < sizeof(fec_t))
|
||||
return -EINVAL;
|
||||
|
||||
memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int get_regs_len(struct net_device *dev)
|
||||
{
|
||||
return sizeof(fec_t);
|
||||
}
|
||||
|
||||
void tx_restart(struct net_device *dev)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
/*************************************************************************/
|
||||
|
||||
const struct fs_ops fs_fec_ops = {
|
||||
.setup_data = setup_data,
|
||||
.cleanup_data = cleanup_data,
|
||||
.set_multicast_list = set_multicast_list,
|
||||
.restart = restart,
|
||||
.stop = stop,
|
||||
.pre_request_irq = pre_request_irq,
|
||||
.post_free_irq = post_free_irq,
|
||||
.napi_clear_rx_event = napi_clear_rx_event,
|
||||
.napi_enable_rx = napi_enable_rx,
|
||||
.napi_disable_rx = napi_disable_rx,
|
||||
.rx_bd_done = rx_bd_done,
|
||||
.tx_kickstart = tx_kickstart,
|
||||
.get_int_events = get_int_events,
|
||||
.clear_int_events = clear_int_events,
|
||||
.ev_error = ev_error,
|
||||
.get_regs = get_regs,
|
||||
.get_regs_len = get_regs_len,
|
||||
.tx_restart = tx_restart,
|
||||
.allocate_bd = allocate_bd,
|
||||
.free_bd = free_bd,
|
||||
};
|
||||
|
||||
/***********************************************************************/
|
||||
|
||||
static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
|
||||
{
|
||||
fec_t *fecp = bus->fec.fecp;
|
||||
int i, ret = -1;
|
||||
|
||||
if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
|
||||
BUG();
|
||||
|
||||
/* Add PHY address to register command. */
|
||||
FW(fecp, mii_data, (phy_id << 23) | mk_mii_read(location));
|
||||
|
||||
for (i = 0; i < FEC_MII_LOOPS; i++)
|
||||
if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
|
||||
break;
|
||||
|
||||
if (i < FEC_MII_LOOPS) {
|
||||
FW(fecp, ievent, FEC_ENET_MII);
|
||||
ret = FR(fecp, mii_data) & 0xffff;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int value)
|
||||
{
|
||||
fec_t *fecp = bus->fec.fecp;
|
||||
int i;
|
||||
|
||||
/* this must never happen */
|
||||
if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
|
||||
BUG();
|
||||
|
||||
/* Add PHY address to register command. */
|
||||
FW(fecp, mii_data, (phy_id << 23) | mk_mii_write(location, value));
|
||||
|
||||
for (i = 0; i < FEC_MII_LOOPS; i++)
|
||||
if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
|
||||
break;
|
||||
|
||||
if (i < FEC_MII_LOOPS)
|
||||
FW(fecp, ievent, FEC_ENET_MII);
|
||||
}
|
||||
|
||||
int fs_mii_fec_init(struct fs_enet_mii_bus *bus)
|
||||
{
|
||||
bd_t *bd = (bd_t *)__res;
|
||||
const struct fs_mii_bus_info *bi = bus->bus_info;
|
||||
fec_t *fecp;
|
||||
|
||||
if (bi->id != 0)
|
||||
return -1;
|
||||
|
||||
bus->fec.fecp = &((immap_t *)fs_enet_immap)->im_cpm.cp_fec;
|
||||
bus->fec.mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2)
|
||||
& 0x3F) << 1;
|
||||
|
||||
fecp = bus->fec.fecp;
|
||||
|
||||
FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
|
||||
FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
|
||||
FW(fecp, ievent, FEC_ENET_MII);
|
||||
FW(fecp, mii_speed, bus->fec.mii_speed);
|
||||
|
||||
bus->mii_read = mii_read;
|
||||
bus->mii_write = mii_write;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,524 @@
|
|||
/*
|
||||
* Ethernet on Serial Communications Controller (SCC) driver for Motorola MPC8xx and MPC82xx.
|
||||
*
|
||||
* Copyright (c) 2003 Intracom S.A.
|
||||
* by Pantelis Antoniou <panto@intracom.gr>
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc.
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/fs.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
#ifdef CONFIG_8xx
|
||||
#include <asm/8xx_immap.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mpc8xx.h>
|
||||
#include <asm/commproc.h>
|
||||
#endif
|
||||
|
||||
#include "fs_enet.h"
|
||||
|
||||
/*************************************************/
|
||||
|
||||
#if defined(CONFIG_CPM1)
|
||||
/* for a 8xx __raw_xxx's are sufficient */
|
||||
#define __fs_out32(addr, x) __raw_writel(x, addr)
|
||||
#define __fs_out16(addr, x) __raw_writew(x, addr)
|
||||
#define __fs_out8(addr, x) __raw_writeb(x, addr)
|
||||
#define __fs_in32(addr) __raw_readl(addr)
|
||||
#define __fs_in16(addr) __raw_readw(addr)
|
||||
#define __fs_in8(addr) __raw_readb(addr)
|
||||
#else
|
||||
/* for others play it safe */
|
||||
#define __fs_out32(addr, x) out_be32(addr, x)
|
||||
#define __fs_out16(addr, x) out_be16(addr, x)
|
||||
#define __fs_in32(addr) in_be32(addr)
|
||||
#define __fs_in16(addr) in_be16(addr)
|
||||
#endif
|
||||
|
||||
/* write, read, set bits, clear bits */
|
||||
#define W32(_p, _m, _v) __fs_out32(&(_p)->_m, (_v))
|
||||
#define R32(_p, _m) __fs_in32(&(_p)->_m)
|
||||
#define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v))
|
||||
#define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v))
|
||||
|
||||
#define W16(_p, _m, _v) __fs_out16(&(_p)->_m, (_v))
|
||||
#define R16(_p, _m) __fs_in16(&(_p)->_m)
|
||||
#define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v))
|
||||
#define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v))
|
||||
|
||||
#define W8(_p, _m, _v) __fs_out8(&(_p)->_m, (_v))
|
||||
#define R8(_p, _m) __fs_in8(&(_p)->_m)
|
||||
#define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v))
|
||||
#define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v))
|
||||
|
||||
#define SCC_MAX_MULTICAST_ADDRS 64
|
||||
|
||||
/*
|
||||
* Delay to wait for SCC reset command to complete (in us)
|
||||
*/
|
||||
#define SCC_RESET_DELAY 50
|
||||
#define MAX_CR_CMD_LOOPS 10000
|
||||
|
||||
static inline int scc_cr_cmd(struct fs_enet_private *fep, u32 op)
|
||||
{
|
||||
cpm8xx_t *cpmp = &((immap_t *)fs_enet_immap)->im_cpm;
|
||||
u32 v, ch;
|
||||
int i = 0;
|
||||
|
||||
ch = fep->scc.idx << 2;
|
||||
v = mk_cr_cmd(ch, op);
|
||||
W16(cpmp, cp_cpcr, v | CPM_CR_FLG);
|
||||
for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
|
||||
if ((R16(cpmp, cp_cpcr) & CPM_CR_FLG) == 0)
|
||||
break;
|
||||
|
||||
if (i >= MAX_CR_CMD_LOOPS) {
|
||||
printk(KERN_ERR "%s(): Not able to issue CPM command\n",
|
||||
__FUNCTION__);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_pd_setup(struct fs_enet_private *fep)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(fep->dev);
|
||||
struct resource *r;
|
||||
|
||||
/* Fill out IRQ field */
|
||||
fep->interrupt = platform_get_irq_byname(pdev, "interrupt");
|
||||
|
||||
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
|
||||
fep->scc.sccp = (void *)r->start;
|
||||
|
||||
if (fep->scc.sccp == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pram");
|
||||
fep->scc.ep = (void *)r->start;
|
||||
|
||||
if (fep->scc.ep == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define SCC_NAPI_RX_EVENT_MSK (SCCE_ENET_RXF | SCCE_ENET_RXB)
|
||||
#define SCC_RX_EVENT (SCCE_ENET_RXF)
|
||||
#define SCC_TX_EVENT (SCCE_ENET_TXB)
|
||||
#define SCC_ERR_EVENT_MSK (SCCE_ENET_TXE | SCCE_ENET_BSY)
|
||||
|
||||
static int setup_data(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
|
||||
fep->scc.idx = fs_get_scc_index(fpi->fs_no);
|
||||
if ((unsigned int)fep->fcc.idx > 4) /* max 4 SCCs */
|
||||
return -EINVAL;
|
||||
|
||||
do_pd_setup(fep);
|
||||
|
||||
fep->scc.hthi = 0;
|
||||
fep->scc.htlo = 0;
|
||||
|
||||
fep->ev_napi_rx = SCC_NAPI_RX_EVENT_MSK;
|
||||
fep->ev_rx = SCC_RX_EVENT;
|
||||
fep->ev_tx = SCC_TX_EVENT;
|
||||
fep->ev_err = SCC_ERR_EVENT_MSK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int allocate_bd(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
|
||||
fep->ring_mem_addr = cpm_dpalloc((fpi->tx_ring + fpi->rx_ring) *
|
||||
sizeof(cbd_t), 8);
|
||||
if (IS_DPERR(fep->ring_mem_addr))
|
||||
return -ENOMEM;
|
||||
|
||||
fep->ring_base = cpm_dpram_addr(fep->ring_mem_addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void free_bd(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
|
||||
if (fep->ring_base)
|
||||
cpm_dpfree(fep->ring_mem_addr);
|
||||
}
|
||||
|
||||
static void cleanup_data(struct net_device *dev)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
static void set_promiscuous_mode(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
scc_t *sccp = fep->scc.sccp;
|
||||
|
||||
S16(sccp, scc_psmr, SCC_PSMR_PRO);
|
||||
}
|
||||
|
||||
static void set_multicast_start(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
scc_enet_t *ep = fep->scc.ep;
|
||||
|
||||
W16(ep, sen_gaddr1, 0);
|
||||
W16(ep, sen_gaddr2, 0);
|
||||
W16(ep, sen_gaddr3, 0);
|
||||
W16(ep, sen_gaddr4, 0);
|
||||
}
|
||||
|
||||
static void set_multicast_one(struct net_device *dev, const u8 * mac)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
scc_enet_t *ep = fep->scc.ep;
|
||||
u16 taddrh, taddrm, taddrl;
|
||||
|
||||
taddrh = ((u16) mac[5] << 8) | mac[4];
|
||||
taddrm = ((u16) mac[3] << 8) | mac[2];
|
||||
taddrl = ((u16) mac[1] << 8) | mac[0];
|
||||
|
||||
W16(ep, sen_taddrh, taddrh);
|
||||
W16(ep, sen_taddrm, taddrm);
|
||||
W16(ep, sen_taddrl, taddrl);
|
||||
scc_cr_cmd(fep, CPM_CR_SET_GADDR);
|
||||
}
|
||||
|
||||
static void set_multicast_finish(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
scc_t *sccp = fep->scc.sccp;
|
||||
scc_enet_t *ep = fep->scc.ep;
|
||||
|
||||
/* clear promiscuous always */
|
||||
C16(sccp, scc_psmr, SCC_PSMR_PRO);
|
||||
|
||||
/* if all multi or too many multicasts; just enable all */
|
||||
if ((dev->flags & IFF_ALLMULTI) != 0 ||
|
||||
dev->mc_count > SCC_MAX_MULTICAST_ADDRS) {
|
||||
|
||||
W16(ep, sen_gaddr1, 0xffff);
|
||||
W16(ep, sen_gaddr2, 0xffff);
|
||||
W16(ep, sen_gaddr3, 0xffff);
|
||||
W16(ep, sen_gaddr4, 0xffff);
|
||||
}
|
||||
}
|
||||
|
||||
static void set_multicast_list(struct net_device *dev)
|
||||
{
|
||||
struct dev_mc_list *pmc;
|
||||
|
||||
if ((dev->flags & IFF_PROMISC) == 0) {
|
||||
set_multicast_start(dev);
|
||||
for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
|
||||
set_multicast_one(dev, pmc->dmi_addr);
|
||||
set_multicast_finish(dev);
|
||||
} else
|
||||
set_promiscuous_mode(dev);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is called to start or restart the FEC during a link
|
||||
* change. This only happens when switching between half and full
|
||||
* duplex.
|
||||
*/
|
||||
static void restart(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
scc_t *sccp = fep->scc.sccp;
|
||||
scc_enet_t *ep = fep->scc.ep;
|
||||
const struct fs_platform_info *fpi = fep->fpi;
|
||||
u16 paddrh, paddrm, paddrl;
|
||||
const unsigned char *mac;
|
||||
int i;
|
||||
|
||||
C32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
|
||||
/* clear everything (slow & steady does it) */
|
||||
for (i = 0; i < sizeof(*ep); i++)
|
||||
__fs_out8((char *)ep + i, 0);
|
||||
|
||||
/* point to bds */
|
||||
W16(ep, sen_genscc.scc_rbase, fep->ring_mem_addr);
|
||||
W16(ep, sen_genscc.scc_tbase,
|
||||
fep->ring_mem_addr + sizeof(cbd_t) * fpi->rx_ring);
|
||||
|
||||
/* Initialize function code registers for big-endian.
|
||||
*/
|
||||
W8(ep, sen_genscc.scc_rfcr, SCC_EB);
|
||||
W8(ep, sen_genscc.scc_tfcr, SCC_EB);
|
||||
|
||||
/* Set maximum bytes per receive buffer.
|
||||
* This appears to be an Ethernet frame size, not the buffer
|
||||
* fragment size. It must be a multiple of four.
|
||||
*/
|
||||
W16(ep, sen_genscc.scc_mrblr, 0x5f0);
|
||||
|
||||
/* Set CRC preset and mask.
|
||||
*/
|
||||
W32(ep, sen_cpres, 0xffffffff);
|
||||
W32(ep, sen_cmask, 0xdebb20e3);
|
||||
|
||||
W32(ep, sen_crcec, 0); /* CRC Error counter */
|
||||
W32(ep, sen_alec, 0); /* alignment error counter */
|
||||
W32(ep, sen_disfc, 0); /* discard frame counter */
|
||||
|
||||
W16(ep, sen_pads, 0x8888); /* Tx short frame pad character */
|
||||
W16(ep, sen_retlim, 15); /* Retry limit threshold */
|
||||
|
||||
W16(ep, sen_maxflr, 0x5ee); /* maximum frame length register */
|
||||
|
||||
W16(ep, sen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */
|
||||
|
||||
W16(ep, sen_maxd1, 0x000005f0); /* maximum DMA1 length */
|
||||
W16(ep, sen_maxd2, 0x000005f0); /* maximum DMA2 length */
|
||||
|
||||
/* Clear hash tables.
|
||||
*/
|
||||
W16(ep, sen_gaddr1, 0);
|
||||
W16(ep, sen_gaddr2, 0);
|
||||
W16(ep, sen_gaddr3, 0);
|
||||
W16(ep, sen_gaddr4, 0);
|
||||
W16(ep, sen_iaddr1, 0);
|
||||
W16(ep, sen_iaddr2, 0);
|
||||
W16(ep, sen_iaddr3, 0);
|
||||
W16(ep, sen_iaddr4, 0);
|
||||
|
||||
/* set address
|
||||
*/
|
||||
mac = dev->dev_addr;
|
||||
paddrh = ((u16) mac[5] << 8) | mac[4];
|
||||
paddrm = ((u16) mac[3] << 8) | mac[2];
|
||||
paddrl = ((u16) mac[1] << 8) | mac[0];
|
||||
|
||||
W16(ep, sen_paddrh, paddrh);
|
||||
W16(ep, sen_paddrm, paddrm);
|
||||
W16(ep, sen_paddrl, paddrl);
|
||||
|
||||
W16(ep, sen_pper, 0);
|
||||
W16(ep, sen_taddrl, 0);
|
||||
W16(ep, sen_taddrm, 0);
|
||||
W16(ep, sen_taddrh, 0);
|
||||
|
||||
fs_init_bds(dev);
|
||||
|
||||
scc_cr_cmd(fep, CPM_CR_INIT_TRX);
|
||||
|
||||
W16(sccp, scc_scce, 0xffff);
|
||||
|
||||
/* Enable interrupts we wish to service.
|
||||
*/
|
||||
W16(sccp, scc_sccm, SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB);
|
||||
|
||||
/* Set GSMR_H to enable all normal operating modes.
|
||||
* Set GSMR_L to enable Ethernet to MC68160.
|
||||
*/
|
||||
W32(sccp, scc_gsmrh, 0);
|
||||
W32(sccp, scc_gsmrl,
|
||||
SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 |
|
||||
SCC_GSMRL_MODE_ENET);
|
||||
|
||||
/* Set sync/delimiters.
|
||||
*/
|
||||
W16(sccp, scc_dsr, 0xd555);
|
||||
|
||||
/* Set processing mode. Use Ethernet CRC, catch broadcast, and
|
||||
* start frame search 22 bit times after RENA.
|
||||
*/
|
||||
W16(sccp, scc_psmr, SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
|
||||
|
||||
/* Set full duplex mode if needed */
|
||||
if (fep->duplex)
|
||||
S16(sccp, scc_psmr, SCC_PSMR_LPB | SCC_PSMR_FDE);
|
||||
|
||||
S32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
}
|
||||
|
||||
static void stop(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
scc_t *sccp = fep->scc.sccp;
|
||||
int i;
|
||||
|
||||
for (i = 0; (R16(sccp, scc_sccm) == 0) && i < SCC_RESET_DELAY; i++)
|
||||
udelay(1);
|
||||
|
||||
if (i == SCC_RESET_DELAY)
|
||||
printk(KERN_WARNING DRV_MODULE_NAME
|
||||
": %s SCC timeout on graceful transmit stop\n",
|
||||
dev->name);
|
||||
|
||||
W16(sccp, scc_sccm, 0);
|
||||
C32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
|
||||
fs_cleanup_bds(dev);
|
||||
}
|
||||
|
||||
static void pre_request_irq(struct net_device *dev, int irq)
|
||||
{
|
||||
immap_t *immap = fs_enet_immap;
|
||||
u32 siel;
|
||||
|
||||
/* SIU interrupt */
|
||||
if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {
|
||||
|
||||
siel = in_be32(&immap->im_siu_conf.sc_siel);
|
||||
if ((irq & 1) == 0)
|
||||
siel |= (0x80000000 >> irq);
|
||||
else
|
||||
siel &= ~(0x80000000 >> (irq & ~1));
|
||||
out_be32(&immap->im_siu_conf.sc_siel, siel);
|
||||
}
|
||||
}
|
||||
|
||||
static void post_free_irq(struct net_device *dev, int irq)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
static void napi_clear_rx_event(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
scc_t *sccp = fep->scc.sccp;
|
||||
|
||||
W16(sccp, scc_scce, SCC_NAPI_RX_EVENT_MSK);
|
||||
}
|
||||
|
||||
static void napi_enable_rx(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
scc_t *sccp = fep->scc.sccp;
|
||||
|
||||
S16(sccp, scc_sccm, SCC_NAPI_RX_EVENT_MSK);
|
||||
}
|
||||
|
||||
static void napi_disable_rx(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
scc_t *sccp = fep->scc.sccp;
|
||||
|
||||
C16(sccp, scc_sccm, SCC_NAPI_RX_EVENT_MSK);
|
||||
}
|
||||
|
||||
static void rx_bd_done(struct net_device *dev)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
static void tx_kickstart(struct net_device *dev)
|
||||
{
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
static u32 get_int_events(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
scc_t *sccp = fep->scc.sccp;
|
||||
|
||||
return (u32) R16(sccp, scc_scce);
|
||||
}
|
||||
|
||||
static void clear_int_events(struct net_device *dev, u32 int_events)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
scc_t *sccp = fep->scc.sccp;
|
||||
|
||||
W16(sccp, scc_scce, int_events & 0xffff);
|
||||
}
|
||||
|
||||
static void ev_error(struct net_device *dev, u32 int_events)
|
||||
{
|
||||
printk(KERN_WARNING DRV_MODULE_NAME
|
||||
": %s SCC ERROR(s) 0x%x\n", dev->name, int_events);
|
||||
}
|
||||
|
||||
static int get_regs(struct net_device *dev, void *p, int *sizep)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
|
||||
if (*sizep < sizeof(scc_t) + sizeof(scc_enet_t))
|
||||
return -EINVAL;
|
||||
|
||||
memcpy_fromio(p, fep->scc.sccp, sizeof(scc_t));
|
||||
p = (char *)p + sizeof(scc_t);
|
||||
|
||||
memcpy_fromio(p, fep->scc.ep, sizeof(scc_enet_t));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_regs_len(struct net_device *dev)
|
||||
{
|
||||
return sizeof(scc_t) + sizeof(scc_enet_t);
|
||||
}
|
||||
|
||||
static void tx_restart(struct net_device *dev)
|
||||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
|
||||
scc_cr_cmd(fep, CPM_CR_RESTART_TX);
|
||||
}
|
||||
|
||||
/*************************************************************************/
|
||||
|
||||
const struct fs_ops fs_scc_ops = {
|
||||
.setup_data = setup_data,
|
||||
.cleanup_data = cleanup_data,
|
||||
.set_multicast_list = set_multicast_list,
|
||||
.restart = restart,
|
||||
.stop = stop,
|
||||
.pre_request_irq = pre_request_irq,
|
||||
.post_free_irq = post_free_irq,
|
||||
.napi_clear_rx_event = napi_clear_rx_event,
|
||||
.napi_enable_rx = napi_enable_rx,
|
||||
.napi_disable_rx = napi_disable_rx,
|
||||
.rx_bd_done = rx_bd_done,
|
||||
.tx_kickstart = tx_kickstart,
|
||||
.get_int_events = get_int_events,
|
||||
.clear_int_events = clear_int_events,
|
||||
.ev_error = ev_error,
|
||||
.get_regs = get_regs,
|
||||
.get_regs_len = get_regs_len,
|
||||
.tx_restart = tx_restart,
|
||||
.allocate_bd = allocate_bd,
|
||||
.free_bd = free_bd,
|
||||
};
|
||||
|
|
@ -0,0 +1,405 @@
|
|||
/*
|
||||
* Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
|
||||
*
|
||||
* Copyright (c) 2003 Intracom S.A.
|
||||
* by Pantelis Antoniou <panto@intracom.gr>
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc.
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
#include "fs_enet.h"
|
||||
|
||||
#ifdef CONFIG_8xx
|
||||
static int bitbang_prep_bit(u8 **dirp, u8 **datp, u8 *mskp, int port, int bit)
|
||||
{
|
||||
immap_t *im = (immap_t *)fs_enet_immap;
|
||||
void *dir, *dat, *ppar;
|
||||
int adv;
|
||||
u8 msk;
|
||||
|
||||
switch (port) {
|
||||
case fsiop_porta:
|
||||
dir = &im->im_ioport.iop_padir;
|
||||
dat = &im->im_ioport.iop_padat;
|
||||
ppar = &im->im_ioport.iop_papar;
|
||||
break;
|
||||
|
||||
case fsiop_portb:
|
||||
dir = &im->im_cpm.cp_pbdir;
|
||||
dat = &im->im_cpm.cp_pbdat;
|
||||
ppar = &im->im_cpm.cp_pbpar;
|
||||
break;
|
||||
|
||||
case fsiop_portc:
|
||||
dir = &im->im_ioport.iop_pcdir;
|
||||
dat = &im->im_ioport.iop_pcdat;
|
||||
ppar = &im->im_ioport.iop_pcpar;
|
||||
break;
|
||||
|
||||
case fsiop_portd:
|
||||
dir = &im->im_ioport.iop_pddir;
|
||||
dat = &im->im_ioport.iop_pddat;
|
||||
ppar = &im->im_ioport.iop_pdpar;
|
||||
break;
|
||||
|
||||
case fsiop_porte:
|
||||
dir = &im->im_cpm.cp_pedir;
|
||||
dat = &im->im_cpm.cp_pedat;
|
||||
ppar = &im->im_cpm.cp_pepar;
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(KERN_ERR DRV_MODULE_NAME
|
||||
"Illegal port value %d!\n", port);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
adv = bit >> 3;
|
||||
dir = (char *)dir + adv;
|
||||
dat = (char *)dat + adv;
|
||||
ppar = (char *)ppar + adv;
|
||||
|
||||
msk = 1 << (7 - (bit & 7));
|
||||
if ((in_8(ppar) & msk) != 0) {
|
||||
printk(KERN_ERR DRV_MODULE_NAME
|
||||
"pin %d on port %d is not general purpose!\n", bit, port);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
*dirp = dir;
|
||||
*datp = dat;
|
||||
*mskp = msk;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_8260
|
||||
static int bitbang_prep_bit(u8 **dirp, u8 **datp, u8 *mskp, int port, int bit)
|
||||
{
|
||||
iop_cpm2_t *io = &((cpm2_map_t *)fs_enet_immap)->im_ioport;
|
||||
void *dir, *dat, *ppar;
|
||||
int adv;
|
||||
u8 msk;
|
||||
|
||||
switch (port) {
|
||||
case fsiop_porta:
|
||||
dir = &io->iop_pdira;
|
||||
dat = &io->iop_pdata;
|
||||
ppar = &io->iop_ppara;
|
||||
break;
|
||||
|
||||
case fsiop_portb:
|
||||
dir = &io->iop_pdirb;
|
||||
dat = &io->iop_pdatb;
|
||||
ppar = &io->iop_pparb;
|
||||
break;
|
||||
|
||||
case fsiop_portc:
|
||||
dir = &io->iop_pdirc;
|
||||
dat = &io->iop_pdatc;
|
||||
ppar = &io->iop_pparc;
|
||||
break;
|
||||
|
||||
case fsiop_portd:
|
||||
dir = &io->iop_pdird;
|
||||
dat = &io->iop_pdatd;
|
||||
ppar = &io->iop_ppard;
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(KERN_ERR DRV_MODULE_NAME
|
||||
"Illegal port value %d!\n", port);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
adv = bit >> 3;
|
||||
dir = (char *)dir + adv;
|
||||
dat = (char *)dat + adv;
|
||||
ppar = (char *)ppar + adv;
|
||||
|
||||
msk = 1 << (7 - (bit & 7));
|
||||
if ((in_8(ppar) & msk) != 0) {
|
||||
printk(KERN_ERR DRV_MODULE_NAME
|
||||
"pin %d on port %d is not general purpose!\n", bit, port);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
*dirp = dir;
|
||||
*datp = dat;
|
||||
*mskp = msk;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void bb_set(u8 *p, u8 m)
|
||||
{
|
||||
out_8(p, in_8(p) | m);
|
||||
}
|
||||
|
||||
static inline void bb_clr(u8 *p, u8 m)
|
||||
{
|
||||
out_8(p, in_8(p) & ~m);
|
||||
}
|
||||
|
||||
static inline int bb_read(u8 *p, u8 m)
|
||||
{
|
||||
return (in_8(p) & m) != 0;
|
||||
}
|
||||
|
||||
static inline void mdio_active(struct fs_enet_mii_bus *bus)
|
||||
{
|
||||
bb_set(bus->bitbang.mdio_dir, bus->bitbang.mdio_msk);
|
||||
}
|
||||
|
||||
static inline void mdio_tristate(struct fs_enet_mii_bus *bus)
|
||||
{
|
||||
bb_clr(bus->bitbang.mdio_dir, bus->bitbang.mdio_msk);
|
||||
}
|
||||
|
||||
static inline int mdio_read(struct fs_enet_mii_bus *bus)
|
||||
{
|
||||
return bb_read(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
|
||||
}
|
||||
|
||||
static inline void mdio(struct fs_enet_mii_bus *bus, int what)
|
||||
{
|
||||
if (what)
|
||||
bb_set(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
|
||||
else
|
||||
bb_clr(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
|
||||
}
|
||||
|
||||
static inline void mdc(struct fs_enet_mii_bus *bus, int what)
|
||||
{
|
||||
if (what)
|
||||
bb_set(bus->bitbang.mdc_dat, bus->bitbang.mdc_msk);
|
||||
else
|
||||
bb_clr(bus->bitbang.mdc_dat, bus->bitbang.mdc_msk);
|
||||
}
|
||||
|
||||
static inline void mii_delay(struct fs_enet_mii_bus *bus)
|
||||
{
|
||||
udelay(bus->bus_info->i.bitbang.delay);
|
||||
}
|
||||
|
||||
/* Utility to send the preamble, address, and register (common to read and write). */
|
||||
static void bitbang_pre(struct fs_enet_mii_bus *bus, int read, u8 addr, u8 reg)
|
||||
{
|
||||
int j;
|
||||
|
||||
/*
|
||||
* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
|
||||
* The IEEE spec says this is a PHY optional requirement. The AMD
|
||||
* 79C874 requires one after power up and one after a MII communications
|
||||
* error. This means that we are doing more preambles than we need,
|
||||
* but it is safer and will be much more robust.
|
||||
*/
|
||||
|
||||
mdio_active(bus);
|
||||
mdio(bus, 1);
|
||||
for (j = 0; j < 32; j++) {
|
||||
mdc(bus, 0);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
}
|
||||
|
||||
/* send the start bit (01) and the read opcode (10) or write (10) */
|
||||
mdc(bus, 0);
|
||||
mdio(bus, 0);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 0);
|
||||
mdio(bus, 1);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 0);
|
||||
mdio(bus, read);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 0);
|
||||
mdio(bus, !read);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
|
||||
/* send the PHY address */
|
||||
for (j = 0; j < 5; j++) {
|
||||
mdc(bus, 0);
|
||||
mdio(bus, (addr & 0x10) != 0);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
addr <<= 1;
|
||||
}
|
||||
|
||||
/* send the register address */
|
||||
for (j = 0; j < 5; j++) {
|
||||
mdc(bus, 0);
|
||||
mdio(bus, (reg & 0x10) != 0);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
reg <<= 1;
|
||||
}
|
||||
}
|
||||
|
||||
static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
|
||||
{
|
||||
u16 rdreg;
|
||||
int ret, j;
|
||||
u8 addr = phy_id & 0xff;
|
||||
u8 reg = location & 0xff;
|
||||
|
||||
bitbang_pre(bus, 1, addr, reg);
|
||||
|
||||
/* tri-state our MDIO I/O pin so we can read */
|
||||
mdc(bus, 0);
|
||||
mdio_tristate(bus);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
|
||||
/* check the turnaround bit: the PHY should be driving it to zero */
|
||||
if (mdio_read(bus) != 0) {
|
||||
/* PHY didn't drive TA low */
|
||||
for (j = 0; j < 32; j++) {
|
||||
mdc(bus, 0);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
}
|
||||
ret = -1;
|
||||
goto out;
|
||||
}
|
||||
|
||||
mdc(bus, 0);
|
||||
mii_delay(bus);
|
||||
|
||||
/* read 16 bits of register data, MSB first */
|
||||
rdreg = 0;
|
||||
for (j = 0; j < 16; j++) {
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
rdreg <<= 1;
|
||||
rdreg |= mdio_read(bus);
|
||||
mdc(bus, 0);
|
||||
mii_delay(bus);
|
||||
}
|
||||
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 0);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
|
||||
ret = rdreg;
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int val)
|
||||
{
|
||||
int j;
|
||||
u8 addr = phy_id & 0xff;
|
||||
u8 reg = location & 0xff;
|
||||
u16 value = val & 0xffff;
|
||||
|
||||
bitbang_pre(bus, 0, addr, reg);
|
||||
|
||||
/* send the turnaround (10) */
|
||||
mdc(bus, 0);
|
||||
mdio(bus, 1);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 0);
|
||||
mdio(bus, 0);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
|
||||
/* write 16 bits of register data, MSB first */
|
||||
for (j = 0; j < 16; j++) {
|
||||
mdc(bus, 0);
|
||||
mdio(bus, (value & 0x8000) != 0);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
value <<= 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Tri-state the MDIO line.
|
||||
*/
|
||||
mdio_tristate(bus);
|
||||
mdc(bus, 0);
|
||||
mii_delay(bus);
|
||||
mdc(bus, 1);
|
||||
mii_delay(bus);
|
||||
}
|
||||
|
||||
int fs_mii_bitbang_init(struct fs_enet_mii_bus *bus)
|
||||
{
|
||||
const struct fs_mii_bus_info *bi = bus->bus_info;
|
||||
int r;
|
||||
|
||||
r = bitbang_prep_bit(&bus->bitbang.mdio_dir,
|
||||
&bus->bitbang.mdio_dat,
|
||||
&bus->bitbang.mdio_msk,
|
||||
bi->i.bitbang.mdio_port,
|
||||
bi->i.bitbang.mdio_bit);
|
||||
if (r != 0)
|
||||
return r;
|
||||
|
||||
r = bitbang_prep_bit(&bus->bitbang.mdc_dir,
|
||||
&bus->bitbang.mdc_dat,
|
||||
&bus->bitbang.mdc_msk,
|
||||
bi->i.bitbang.mdc_port,
|
||||
bi->i.bitbang.mdc_bit);
|
||||
if (r != 0)
|
||||
return r;
|
||||
|
||||
bus->mii_read = mii_read;
|
||||
bus->mii_write = mii_write;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
|
||||
*
|
||||
* Copyright (c) 2003 Intracom S.A.
|
||||
* by Pantelis Antoniou <panto@intracom.gr>
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc.
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
#include "fs_enet.h"
|
||||
|
||||
static const u16 mii_regs[7] = {
|
||||
0x3100,
|
||||
0x786d,
|
||||
0x0fff,
|
||||
0x0fff,
|
||||
0x01e1,
|
||||
0x45e1,
|
||||
0x0003,
|
||||
};
|
||||
|
||||
static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if ((unsigned int)location >= ARRAY_SIZE(mii_regs))
|
||||
return -1;
|
||||
|
||||
if (location != 5)
|
||||
ret = mii_regs[location];
|
||||
else
|
||||
ret = bus->fixed.lpa;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int val)
|
||||
{
|
||||
/* do nothing */
|
||||
}
|
||||
|
||||
int fs_mii_fixed_init(struct fs_enet_mii_bus *bus)
|
||||
{
|
||||
const struct fs_mii_bus_info *bi = bus->bus_info;
|
||||
|
||||
bus->fixed.lpa = 0x45e1; /* default 100Mb, full duplex */
|
||||
|
||||
/* if speed is fixed at 10Mb, remove 100Mb modes */
|
||||
if (bi->i.fixed.speed == 10)
|
||||
bus->fixed.lpa &= ~LPA_100;
|
||||
|
||||
/* if duplex is half, remove full duplex modes */
|
||||
if (bi->i.fixed.duplex == 0)
|
||||
bus->fixed.lpa &= ~LPA_DUPLEX;
|
||||
|
||||
bus->mii_read = mii_read;
|
||||
bus->mii_write = mii_write;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Platform information definitions for the
|
||||
* universal Freescale Ethernet driver.
|
||||
*
|
||||
* Copyright (c) 2003 Intracom S.A.
|
||||
* by Pantelis Antoniou <panto@intracom.gr>
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc.
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef FS_ENET_PD_H
|
||||
#define FS_ENET_PD_H
|
||||
|
||||
#include <linux/version.h>
|
||||
#include <asm/types.h>
|
||||
|
||||
#define FS_ENET_NAME "fs_enet"
|
||||
|
||||
enum fs_id {
|
||||
fsid_fec1,
|
||||
fsid_fec2,
|
||||
fsid_fcc1,
|
||||
fsid_fcc2,
|
||||
fsid_fcc3,
|
||||
fsid_scc1,
|
||||
fsid_scc2,
|
||||
fsid_scc3,
|
||||
fsid_scc4,
|
||||
};
|
||||
|
||||
#define FS_MAX_INDEX 9
|
||||
|
||||
static inline int fs_get_fec_index(enum fs_id id)
|
||||
{
|
||||
if (id >= fsid_fec1 && id <= fsid_fec2)
|
||||
return id - fsid_fec1;
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline int fs_get_fcc_index(enum fs_id id)
|
||||
{
|
||||
if (id >= fsid_fcc1 && id <= fsid_fcc3)
|
||||
return id - fsid_fcc1;
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline int fs_get_scc_index(enum fs_id id)
|
||||
{
|
||||
if (id >= fsid_scc1 && id <= fsid_scc4)
|
||||
return id - fsid_scc1;
|
||||
return -1;
|
||||
}
|
||||
|
||||
enum fs_mii_method {
|
||||
fsmii_fixed,
|
||||
fsmii_fec,
|
||||
fsmii_bitbang,
|
||||
};
|
||||
|
||||
enum fs_ioport {
|
||||
fsiop_porta,
|
||||
fsiop_portb,
|
||||
fsiop_portc,
|
||||
fsiop_portd,
|
||||
fsiop_porte,
|
||||
};
|
||||
|
||||
struct fs_mii_bus_info {
|
||||
int method; /* mii method */
|
||||
int id; /* the id of the mii_bus */
|
||||
int disable_aneg; /* if the controller needs to negothiate speed & duplex */
|
||||
int lpa; /* the default board-specific vallues will be applied otherwise */
|
||||
|
||||
union {
|
||||
struct {
|
||||
int duplex;
|
||||
int speed;
|
||||
} fixed;
|
||||
|
||||
struct {
|
||||
/* nothing */
|
||||
} fec;
|
||||
|
||||
struct {
|
||||
/* nothing */
|
||||
} scc;
|
||||
|
||||
struct {
|
||||
int mdio_port; /* port & bit for MDIO */
|
||||
int mdio_bit;
|
||||
int mdc_port; /* port & bit for MDC */
|
||||
int mdc_bit;
|
||||
int delay; /* delay in us */
|
||||
} bitbang;
|
||||
} i;
|
||||
};
|
||||
|
||||
struct fs_platform_info {
|
||||
|
||||
void(*init_ioports)(void);
|
||||
/* device specific information */
|
||||
int fs_no; /* controller index */
|
||||
|
||||
u32 cp_page; /* CPM page */
|
||||
u32 cp_block; /* CPM sblock */
|
||||
|
||||
u32 clk_trx; /* some stuff for pins & mux configuration*/
|
||||
u32 clk_route;
|
||||
u32 clk_mask;
|
||||
|
||||
u32 mem_offset;
|
||||
u32 dpram_offset;
|
||||
u32 fcc_regs_c;
|
||||
|
||||
u32 device_flags;
|
||||
|
||||
int phy_addr; /* the phy address (-1 no phy) */
|
||||
int phy_irq; /* the phy irq (if it exists) */
|
||||
|
||||
const struct fs_mii_bus_info *bus_info;
|
||||
|
||||
int rx_ring, tx_ring; /* number of buffers on rx */
|
||||
__u8 macaddr[6]; /* mac address */
|
||||
int rx_copybreak; /* limit we copy small frames */
|
||||
int use_napi; /* use NAPI */
|
||||
int napi_weight; /* NAPI weight */
|
||||
|
||||
int use_rmii; /* use RMII mode */
|
||||
};
|
||||
|
||||
#endif
|
||||
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