KVM/arm64 fixes for 5.18, take #2
- Take care of faults occuring between the PARange and IPA range by injecting an exception - Fix S2 faults taken from a host EL0 in protected mode - Work around Oops caused by a PMU access from a 32bit guest when PMU has been created. This is a temporary bodge until we fix it for good. -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAmJsA9kPHG1hekBrZXJu ZWwub3JnAAoJECPQ0LrRPXpD/FYP/1G0ctyOaZDWC90sZVtBmVfO9Sc1xiZ2Kael 3+79N96ncFHp8oKTDz4zcSvs2hDG+9tUhG54MVr1DnPuO5rQubEGr+inYnb1cQfr j0qBxvVAyP9wnQmtPeTvbHJCumB3RCm5d1tDLhmr4vnh5vBOn36fpCEhKhuv/2ib xsXE8rhL0PjRV+NV5KAlO5bJuUU0F8OaZ8612yyO0ExtV+6t1WQGsIBhf3aBRhAY oaYG2CmSgsifW9fgXdz/CVzRdPGV4E/hhAcQbY3CmzMbzlO6tqbOIK1NoMivoNIg smKMJNhnaVLSybprAcQvAG9H1vbGSQWLurd42EvZIzn59+ILFHW90fYmW4QM69P3 mqOW40RXlZ/8BwIVEftzyZ8J8XNTpaDeGZ4D1aHY6yvKTd7ApiiU3OZOrYgZ7H/a d/2W3tQfV9MlifJjNFZDWj8fMqxLifcZksvMfwbl775B/9SO66UHx00qFhZxQ5nI 7A8RKyB2jRRM/ndb337XMWoHQVwjof4CUZG1XuLSyYtb1K9joROoLD0hiNYTJOek QxT3T+g5FF3YpxrB270lKA4xJ6fUqUgAisThY5AZnK3Ezw8udx18ADT+X76/OqqQ GTxG3v45YObjA2t4xSk8TszFg83JubsCGKYQLKEbdMsfBIkhvT+fyrW4fCxODGHH r/rK7iuK =Ejoh -----END PGP SIGNATURE----- Merge tag 'kvmarm-fixes-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 fixes for 5.18, take #2 - Take care of faults occuring between the PARange and IPA range by injecting an exception - Fix S2 faults taken from a host EL0 in protected mode - Work around Oops caused by a PMU access from a 32bit guest when PMU has been created. This is a temporary bodge until we fix it for good.
This commit is contained in:
Paolo Bonzini
Коммит
484c22df5a
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@ -40,6 +40,7 @@ void kvm_inject_undefined(struct kvm_vcpu *vcpu);
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void kvm_inject_vabt(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_size_fault(struct kvm_vcpu *vcpu);
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void kvm_vcpu_wfi(struct kvm_vcpu *vcpu);
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@ -198,15 +198,15 @@ SYM_CODE_START(__kvm_hyp_host_vector)
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invalid_host_el2_vect // FIQ EL2h
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invalid_host_el2_vect // Error EL2h
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host_el1_sync_vect // Synchronous 64-bit EL1
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invalid_host_el1_vect // IRQ 64-bit EL1
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invalid_host_el1_vect // FIQ 64-bit EL1
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invalid_host_el1_vect // Error 64-bit EL1
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host_el1_sync_vect // Synchronous 64-bit EL1/EL0
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invalid_host_el1_vect // IRQ 64-bit EL1/EL0
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invalid_host_el1_vect // FIQ 64-bit EL1/EL0
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invalid_host_el1_vect // Error 64-bit EL1/EL0
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invalid_host_el1_vect // Synchronous 32-bit EL1
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invalid_host_el1_vect // IRQ 32-bit EL1
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invalid_host_el1_vect // FIQ 32-bit EL1
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invalid_host_el1_vect // Error 32-bit EL1
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host_el1_sync_vect // Synchronous 32-bit EL1/EL0
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invalid_host_el1_vect // IRQ 32-bit EL1/EL0
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invalid_host_el1_vect // FIQ 32-bit EL1/EL0
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invalid_host_el1_vect // Error 32-bit EL1/EL0
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SYM_CODE_END(__kvm_hyp_host_vector)
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/*
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@ -145,6 +145,34 @@ void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
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inject_abt64(vcpu, true, addr);
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}
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void kvm_inject_size_fault(struct kvm_vcpu *vcpu)
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{
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unsigned long addr, esr;
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addr = kvm_vcpu_get_fault_ipa(vcpu);
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addr |= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
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if (kvm_vcpu_trap_is_iabt(vcpu))
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kvm_inject_pabt(vcpu, addr);
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else
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kvm_inject_dabt(vcpu, addr);
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/*
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* If AArch64 or LPAE, set FSC to 0 to indicate an Address
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* Size Fault at level 0, as if exceeding PARange.
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*
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* Non-LPAE guests will only get the external abort, as there
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* is no way to to describe the ASF.
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*/
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if (vcpu_el1_is_32bit(vcpu) &&
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!(vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE))
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return;
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esr = vcpu_read_sys_reg(vcpu, ESR_EL1);
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esr &= ~GENMASK_ULL(5, 0);
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vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
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}
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/**
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* kvm_inject_undefined - inject an undefined instruction into the guest
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* @vcpu: The vCPU in which to inject the exception
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@ -1337,6 +1337,25 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu)
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fault_ipa = kvm_vcpu_get_fault_ipa(vcpu);
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is_iabt = kvm_vcpu_trap_is_iabt(vcpu);
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if (fault_status == FSC_FAULT) {
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/* Beyond sanitised PARange (which is the IPA limit) */
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if (fault_ipa >= BIT_ULL(get_kvm_ipa_limit())) {
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kvm_inject_size_fault(vcpu);
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return 1;
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}
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/* Falls between the IPA range and the PARange? */
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if (fault_ipa >= BIT_ULL(vcpu->arch.hw_mmu->pgt->ia_bits)) {
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fault_ipa |= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
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if (is_iabt)
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kvm_inject_pabt(vcpu, fault_ipa);
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else
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kvm_inject_dabt(vcpu, fault_ipa);
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return 1;
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}
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}
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/* Synchronous External Abort? */
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if (kvm_vcpu_abt_issea(vcpu)) {
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/*
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@ -177,6 +177,9 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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struct kvm_pmc *pmc = &pmu->pmc[select_idx];
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if (!kvm_vcpu_has_pmu(vcpu))
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return 0;
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counter = kvm_pmu_get_pair_counter_value(vcpu, pmc);
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if (kvm_pmu_pmc_is_chained(pmc) &&
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@ -198,6 +201,9 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val)
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{
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u64 reg;
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if (!kvm_vcpu_has_pmu(vcpu))
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return;
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reg = (select_idx == ARMV8_PMU_CYCLE_IDX)
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? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx;
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__vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx);
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@ -322,6 +328,9 @@ void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val)
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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struct kvm_pmc *pmc;
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if (!kvm_vcpu_has_pmu(vcpu))
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return;
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if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) || !val)
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return;
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@ -357,7 +366,7 @@ void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val)
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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struct kvm_pmc *pmc;
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if (!val)
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if (!kvm_vcpu_has_pmu(vcpu) || !val)
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return;
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for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {
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@ -527,6 +536,9 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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int i;
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if (!kvm_vcpu_has_pmu(vcpu))
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return;
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if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E))
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return;
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@ -576,6 +588,9 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
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{
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int i;
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if (!kvm_vcpu_has_pmu(vcpu))
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return;
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if (val & ARMV8_PMU_PMCR_E) {
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kvm_pmu_enable_counter_mask(vcpu,
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__vcpu_sys_reg(vcpu, PMCNTENSET_EL0));
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@ -739,6 +754,9 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
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{
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u64 reg, mask;
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if (!kvm_vcpu_has_pmu(vcpu))
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return;
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mask = ARMV8_PMU_EVTYPE_MASK;
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mask &= ~ARMV8_PMU_EVTYPE_EVENT;
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mask |= kvm_pmu_event_mask(vcpu->kvm);
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@ -827,6 +845,9 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
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u64 val, mask = 0;
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int base, i, nr_events;
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if (!kvm_vcpu_has_pmu(vcpu))
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return 0;
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if (!pmceid1) {
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val = read_sysreg(pmceid0_el0);
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base = 0;
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