cpufreq: mediatek-hw: Add support for CPUFREQ HW
Introduce cpufreq HW driver which can support CPU frequency adjust in MT6779 platform. Signed-off-by: Hector.Yuan <hector.yuan@mediatek.com> [ Viresh: Massaged the patch and cleaned some stuff. ] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This commit is contained in:
Hector.Yuan
Viresh Kumar
Родитель
8486a32dd4
Коммит
4855e26bcf
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@ -133,6 +133,18 @@ config ARM_MEDIATEK_CPUFREQ
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help
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This adds the CPUFreq driver support for MediaTek SoCs.
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config ARM_MEDIATEK_CPUFREQ_HW
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tristate "MediaTek CPUFreq HW driver"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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default m
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help
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Support for the CPUFreq HW driver.
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Some MediaTek chipsets have a HW engine to offload the steps
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necessary for changing the frequency of the CPUs. Firmware loaded
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in this engine exposes a programming interface to the OS.
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The driver implements the cpufreq interface for this HW engine.
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Say Y if you want to support CPUFreq HW.
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config ARM_OMAP2PLUS_CPUFREQ
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bool "TI OMAP2+"
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depends on ARCH_OMAP2PLUS
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@ -56,6 +56,7 @@ obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
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obj-$(CONFIG_ARM_IMX_CPUFREQ_DT) += imx-cpufreq-dt.o
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obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
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obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
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obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ_HW) += mediatek-cpufreq-hw.o
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obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
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obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
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obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
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@ -0,0 +1,308 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/cpufreq.h>
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#include <linux/energy_model.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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#define LUT_MAX_ENTRIES 32U
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#define LUT_FREQ GENMASK(11, 0)
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#define LUT_ROW_SIZE 0x4
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#define CPUFREQ_HW_STATUS BIT(0)
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#define SVS_HW_STATUS BIT(1)
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#define POLL_USEC 1000
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#define TIMEOUT_USEC 300000
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enum {
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REG_FREQ_LUT_TABLE,
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REG_FREQ_ENABLE,
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REG_FREQ_PERF_STATE,
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REG_FREQ_HW_STATE,
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REG_EM_POWER_TBL,
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REG_FREQ_LATENCY,
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REG_ARRAY_SIZE,
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};
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struct mtk_cpufreq_data {
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struct cpufreq_frequency_table *table;
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void __iomem *reg_bases[REG_ARRAY_SIZE];
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int nr_opp;
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};
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static const u16 cpufreq_mtk_offsets[REG_ARRAY_SIZE] = {
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[REG_FREQ_LUT_TABLE] = 0x0,
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[REG_FREQ_ENABLE] = 0x84,
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[REG_FREQ_PERF_STATE] = 0x88,
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[REG_FREQ_HW_STATE] = 0x8c,
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[REG_EM_POWER_TBL] = 0x90,
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[REG_FREQ_LATENCY] = 0x110,
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};
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static int __maybe_unused
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mtk_cpufreq_get_cpu_power(unsigned long *mW,
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unsigned long *KHz, struct device *cpu_dev)
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{
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struct mtk_cpufreq_data *data;
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struct cpufreq_policy *policy;
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int i;
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policy = cpufreq_cpu_get_raw(cpu_dev->id);
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if (!policy)
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return 0;
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data = policy->driver_data;
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for (i = 0; i < data->nr_opp; i++) {
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if (data->table[i].frequency < *KHz)
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break;
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}
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i--;
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*KHz = data->table[i].frequency;
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*mW = readl_relaxed(data->reg_bases[REG_EM_POWER_TBL] +
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i * LUT_ROW_SIZE) / 1000;
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return 0;
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}
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static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct mtk_cpufreq_data *data = policy->driver_data;
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writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]);
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return 0;
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}
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static unsigned int mtk_cpufreq_hw_get(unsigned int cpu)
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{
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struct mtk_cpufreq_data *data;
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struct cpufreq_policy *policy;
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unsigned int index;
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policy = cpufreq_cpu_get_raw(cpu);
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if (!policy)
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return 0;
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data = policy->driver_data;
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index = readl_relaxed(data->reg_bases[REG_FREQ_PERF_STATE]);
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index = min(index, LUT_MAX_ENTRIES - 1);
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return data->table[index].frequency;
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}
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static unsigned int mtk_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
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unsigned int target_freq)
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{
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struct mtk_cpufreq_data *data = policy->driver_data;
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unsigned int index;
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index = cpufreq_table_find_index_dl(policy, target_freq);
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writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]);
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return policy->freq_table[index].frequency;
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}
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static int mtk_cpu_create_freq_table(struct platform_device *pdev,
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struct mtk_cpufreq_data *data)
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{
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struct device *dev = &pdev->dev;
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u32 temp, i, freq, prev_freq = 0;
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void __iomem *base_table;
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data->table = devm_kcalloc(dev, LUT_MAX_ENTRIES + 1,
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sizeof(*data->table), GFP_KERNEL);
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if (!data->table)
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return -ENOMEM;
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base_table = data->reg_bases[REG_FREQ_LUT_TABLE];
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for (i = 0; i < LUT_MAX_ENTRIES; i++) {
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temp = readl_relaxed(base_table + (i * LUT_ROW_SIZE));
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freq = FIELD_GET(LUT_FREQ, temp) * 1000;
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if (freq == prev_freq)
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break;
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data->table[i].frequency = freq;
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dev_dbg(dev, "index=%d freq=%d\n", i, data->table[i].frequency);
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prev_freq = freq;
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}
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data->table[i].frequency = CPUFREQ_TABLE_END;
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data->nr_opp = i;
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return 0;
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}
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static int mtk_cpu_resources_init(struct platform_device *pdev,
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struct cpufreq_policy *policy,
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const u16 *offsets)
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{
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struct mtk_cpufreq_data *data;
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struct device *dev = &pdev->dev;
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void __iomem *base;
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int ret, i;
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int index;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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index = of_perf_domain_get_sharing_cpumask(policy->cpu, "performance-domains",
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"#performance-domain-cells",
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policy->cpus);
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if (index < 0)
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return index;
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base = devm_platform_ioremap_resource(pdev, index);
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if (IS_ERR(base))
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return PTR_ERR(base);
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for (i = REG_FREQ_LUT_TABLE; i < REG_ARRAY_SIZE; i++)
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data->reg_bases[i] = base + offsets[i];
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ret = mtk_cpu_create_freq_table(pdev, data);
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if (ret) {
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dev_info(dev, "Domain-%d failed to create freq table\n", index);
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return ret;
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}
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policy->freq_table = data->table;
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policy->driver_data = data;
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return 0;
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}
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static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
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{
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struct platform_device *pdev = cpufreq_get_driver_data();
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int sig, pwr_hw = CPUFREQ_HW_STATUS | SVS_HW_STATUS;
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struct mtk_cpufreq_data *data;
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unsigned int latency;
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int ret;
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/* Get the bases of cpufreq for domains */
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ret = mtk_cpu_resources_init(pdev, policy, platform_get_drvdata(pdev));
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if (ret) {
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dev_info(&pdev->dev, "CPUFreq resource init failed\n");
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return ret;
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}
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data = policy->driver_data;
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latency = readl_relaxed(data->reg_bases[REG_FREQ_LATENCY]) * 1000;
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if (!latency)
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latency = CPUFREQ_ETERNAL;
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policy->cpuinfo.transition_latency = latency;
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policy->fast_switch_possible = true;
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/* HW should be in enabled state to proceed now */
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writel_relaxed(0x1, data->reg_bases[REG_FREQ_ENABLE]);
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if (readl_poll_timeout(data->reg_bases[REG_FREQ_HW_STATE], sig,
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(sig & pwr_hw) == pwr_hw, POLL_USEC,
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TIMEOUT_USEC)) {
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if (!(sig & CPUFREQ_HW_STATUS)) {
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pr_info("cpufreq hardware of CPU%d is not enabled\n",
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policy->cpu);
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return -ENODEV;
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}
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pr_info("SVS of CPU%d is not enabled\n", policy->cpu);
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}
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return 0;
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}
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static int mtk_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
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{
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struct mtk_cpufreq_data *data = policy->driver_data;
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/* HW should be in paused state now */
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writel_relaxed(0x0, data->reg_bases[REG_FREQ_ENABLE]);
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return 0;
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}
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static void mtk_cpufreq_register_em(struct cpufreq_policy *policy)
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{
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struct em_data_callback em_cb = EM_DATA_CB(mtk_cpufreq_get_cpu_power);
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struct mtk_cpufreq_data *data = policy->driver_data;
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em_dev_register_perf_domain(get_cpu_device(policy->cpu), data->nr_opp,
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&em_cb, policy->cpus, true);
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}
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static struct cpufreq_driver cpufreq_mtk_hw_driver = {
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.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
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CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
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CPUFREQ_IS_COOLING_DEV,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = mtk_cpufreq_hw_target_index,
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.get = mtk_cpufreq_hw_get,
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.init = mtk_cpufreq_hw_cpu_init,
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.exit = mtk_cpufreq_hw_cpu_exit,
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.register_em = mtk_cpufreq_register_em,
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.fast_switch = mtk_cpufreq_hw_fast_switch,
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.name = "mtk-cpufreq-hw",
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.attr = cpufreq_generic_attr,
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};
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static int mtk_cpufreq_hw_driver_probe(struct platform_device *pdev)
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{
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const void *data;
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int ret;
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data = of_device_get_match_data(&pdev->dev);
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if (!data)
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return -EINVAL;
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platform_set_drvdata(pdev, (void *) data);
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cpufreq_mtk_hw_driver.driver_data = pdev;
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ret = cpufreq_register_driver(&cpufreq_mtk_hw_driver);
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if (ret)
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dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
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return ret;
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}
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static int mtk_cpufreq_hw_driver_remove(struct platform_device *pdev)
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{
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return cpufreq_unregister_driver(&cpufreq_mtk_hw_driver);
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}
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static const struct of_device_id mtk_cpufreq_hw_match[] = {
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{ .compatible = "mediatek,cpufreq-hw", .data = &cpufreq_mtk_offsets },
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{}
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};
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static struct platform_driver mtk_cpufreq_hw_driver = {
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.probe = mtk_cpufreq_hw_driver_probe,
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.remove = mtk_cpufreq_hw_driver_remove,
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.driver = {
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.name = "mtk-cpufreq-hw",
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.of_match_table = mtk_cpufreq_hw_match,
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},
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};
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module_platform_driver(mtk_cpufreq_hw_driver);
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MODULE_AUTHOR("Hector Yuan <hector.yuan@mediatek.com>");
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MODULE_DESCRIPTION("Mediatek cpufreq-hw driver");
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MODULE_LICENSE("GPL v2");
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