cirrusfb: do not change MCLK for Alpine chips
A memory clock value (MCLK) is changed to a minimum required by a current mode bandwidth. This usually lowers the MCLK to its minimum (50 MHz) thus decreasing the card performance. Just leave the MCLK value set by card BIOS. The CL-GD5446 Technical Reference Manual point 9.9.1.3 states that if a pixclock value is close (~1%) to the MCLK or MCLK/2 this may result in a jitter on the screen. A countermeasure is to use the MCLK as pixclock source instead of a VCLK. The patch implements this as well. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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3b921832d4
Коммит
486ff387c0
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@ -327,9 +327,7 @@ static const struct {
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#endif /* CONFIG_ZORRO */
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#endif /* CONFIG_ZORRO */
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struct cirrusfb_regs {
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struct cirrusfb_regs {
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long multiplexing;
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int multiplexing;
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long mclk;
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long divMCLK;
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};
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};
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#ifdef CIRRUSFB_DEBUG
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#ifdef CIRRUSFB_DEBUG
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@ -461,45 +459,28 @@ static int cirrusfb_release(struct fb_info *info, int user)
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/****************************************************************************/
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/****************************************************************************/
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/**** BEGIN Hardware specific Routines **************************************/
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/**** BEGIN Hardware specific Routines **************************************/
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/* Get a good MCLK value */
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/* Check if the MCLK is not a better clock source */
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static long cirrusfb_get_mclk(long freq, int bpp, long *div)
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static int cirrusfb_check_mclk(struct cirrusfb_info *cinfo, long freq)
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{
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{
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long mclk;
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long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
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assert(div != NULL);
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/* Read MCLK value */
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mclk = (14318 * mclk) >> 3;
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/* Calculate MCLK, in case VCLK is high enough to require > 50MHz.
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DPRINTK("Read MCLK of %ld kHz\n", mclk);
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* Assume a 64-bit data path for now. The formula is:
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* ((B * PCLK * 2)/W) * 1.2
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* B = bytes per pixel, PCLK = pixclock, W = data width in bytes */
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mclk = ((bpp / 8) * freq * 2) / 4;
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mclk = (mclk * 12) / 10;
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if (mclk < 50000)
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mclk = 50000;
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DPRINTK("Use MCLK of %ld kHz\n", mclk);
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/* Calculate value for SR1F. Multiply by 2 so we can round up. */
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mclk = ((mclk * 16) / 14318);
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mclk = (mclk + 1) / 2;
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DPRINTK("Set SR1F[5:0] to 0x%lx\n", mclk);
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/* Determine if we should use MCLK instead of VCLK, and if so, what we
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/* Determine if we should use MCLK instead of VCLK, and if so, what we
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* should divide it by to get VCLK */
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* should divide it by to get VCLK
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switch (freq) {
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*/
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case 24751 ... 25249:
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*div = 2;
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if (abs(freq - mclk) < 250) {
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DPRINTK("Using VCLK = MCLK/2\n");
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break;
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case 49501 ... 50499:
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*div = 1;
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DPRINTK("Using VCLK = MCLK\n");
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DPRINTK("Using VCLK = MCLK\n");
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break;
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return 1;
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default:
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} else if (abs(freq - (mclk / 2)) < 250) {
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*div = 0;
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DPRINTK("Using VCLK = MCLK/2\n");
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break;
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return 2;
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}
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}
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return mclk;
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return 0;
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}
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}
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static int cirrusfb_check_var(struct fb_var_screeninfo *var,
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static int cirrusfb_check_var(struct fb_var_screeninfo *var,
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@ -705,30 +686,27 @@ static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
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break;
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break;
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}
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}
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#endif
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#endif
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regs->mclk = cirrusfb_get_mclk(freq, var->bits_per_pixel,
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®s->divMCLK);
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return 0;
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return 0;
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}
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}
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static void cirrusfb_set_mclk(const struct cirrusfb_info *cinfo, int val,
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static void cirrusfb_set_mclk_as_source(const struct cirrusfb_info *cinfo,
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int div)
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int div)
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{
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{
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unsigned char old1f, old1e;
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assert(cinfo != NULL);
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assert(cinfo != NULL);
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old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
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if (div == 2) {
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if (div) {
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/* VCLK = MCLK/2 */
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DPRINTK("Set %s as pixclock source.\n",
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unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
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(div == 2) ? "MCLK/2" : "MCLK");
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vga_wseq(cinfo->regbase, CL_SEQR1E, old | 0x1);
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old1f |= 0x40;
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vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
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old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
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} else if (div == 1) {
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if (div == 2)
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/* VCLK = MCLK */
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old1e |= 1;
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unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
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vga_wseq(cinfo->regbase, CL_SEQR1E, old & ~0x1);
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vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
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vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
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} else {
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vga_wseq(cinfo->regbase, CL_SEQR1F, val & 0x3f);
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}
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}
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vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
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}
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}
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/*************************************************************************
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/*************************************************************************
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@ -904,19 +882,31 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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/* formula: VClk = (OSC * N) / (D * (1+P)) */
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/* formula: VClk = (OSC * N) / (D * (1+P)) */
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/* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
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/* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
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vga_wseq(regbase, CL_SEQRB, nom);
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if (cinfo->btype == BT_ALPINE) {
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tmp = den << 1;
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/* if freq is close to mclk or mclk/2 select mclk
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if (div != 0)
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* as clock source
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tmp |= 1;
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*/
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int divMCLK = cirrusfb_check_mclk(cinfo, freq);
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if (divMCLK) {
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nom = 0;
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cirrusfb_set_mclk_as_source(cinfo, divMCLK);
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}
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}
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if (nom) {
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vga_wseq(regbase, CL_SEQRB, nom);
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tmp = den << 1;
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if (div != 0)
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tmp |= 1;
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/* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
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/* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
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if ((cinfo->btype == BT_SD64) ||
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if ((cinfo->btype == BT_SD64) ||
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(cinfo->btype == BT_ALPINE) ||
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(cinfo->btype == BT_ALPINE) ||
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(cinfo->btype == BT_GD5480))
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(cinfo->btype == BT_GD5480))
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tmp |= 0x80;
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tmp |= 0x80;
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DPRINTK("CL_SEQR1B: %ld\n", (long) tmp);
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DPRINTK("CL_SEQR1B: %ld\n", (long) tmp);
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vga_wseq(regbase, CL_SEQR1B, tmp);
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vga_wseq(regbase, CL_SEQR1B, tmp);
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}
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if (yres >= 1024)
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if (yres >= 1024)
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/* 1280x1024 */
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/* 1280x1024 */
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@ -1106,7 +1096,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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case BT_ALPINE:
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case BT_ALPINE:
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DPRINTK(" (for GD543x)\n");
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DPRINTK(" (for GD543x)\n");
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cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
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/* We already set SRF and SR1F */
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/* We already set SRF and SR1F */
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break;
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break;
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@ -1179,7 +1168,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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case BT_ALPINE:
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case BT_ALPINE:
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DPRINTK(" (for GD543x)\n");
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DPRINTK(" (for GD543x)\n");
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vga_wseq(regbase, CL_SEQR7, 0xa7);
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vga_wseq(regbase, CL_SEQR7, 0xa7);
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cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
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break;
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break;
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case BT_GD5480:
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case BT_GD5480:
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@ -1257,7 +1245,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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case BT_ALPINE:
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case BT_ALPINE:
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DPRINTK(" (for GD543x)\n");
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DPRINTK(" (for GD543x)\n");
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vga_wseq(regbase, CL_SEQR7, 0xa9);
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vga_wseq(regbase, CL_SEQR7, 0xa9);
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cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
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break;
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break;
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case BT_GD5480:
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case BT_GD5480:
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