From 901d51435c31f9c3147efa64e379bf00208bde01 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 4 Sep 2019 17:02:20 -0700 Subject: [PATCH 1/6] ARM: dts: aspeed-g4: Add all flash chips The FMC supports five chip selects, so describe the five possible flash chips. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index e465cda40fe7..dffb595d30e4 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -67,6 +67,26 @@ compatible = "jedec,spi-nor"; status = "disabled"; }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@3 { + reg = < 3 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@4 { + reg = < 4 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; }; spi: spi@1e630000 { From 9d463f8a180bbee1bec4583a5691375ea32a1d6b Mon Sep 17 00:00:00 2001 From: Ivan Mikhaylov Date: Wed, 28 Aug 2019 13:23:59 +0300 Subject: [PATCH 2/6] ARM: dts: aspeed: vesnin: Add wdt2 with alt-boot option Adds wdt2 section with 'alt-boot' option into dts for vesnin. Signed-off-by: Ivan Mikhaylov Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts index 0b9e29c3212e..2ee26c86a32e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts @@ -222,3 +222,7 @@ &vuart { status = "okay"; }; + +&wdt2 { + aspeed,alt-boot; +}; From 659b7a4bd797597febd03c0fb7a286ee4da16732 Mon Sep 17 00:00:00 2001 From: Ivan Mikhaylov Date: Wed, 28 Aug 2019 13:24:00 +0300 Subject: [PATCH 3/6] ARM: dts: aspeed: vesnin: Add secondary SPI flash chip Adds secondary SPI flash chip into dts for vesnin. Signed-off-by: Ivan Mikhaylov Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts index 2ee26c86a32e..a27c88d23056 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts @@ -81,6 +81,12 @@ label = "bmc"; #include "openbmc-flash-layout.dtsi" }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt"; + }; }; &spi { From 020cdf3a51f666ccd980fe79a4586b22363d3984 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Fri, 30 Aug 2019 14:11:02 -0500 Subject: [PATCH 4/6] ARM: dts: aspeed: swift: Change power supplies to version 2 Swift power supplies are version 2 of the IBM CFFPS. Fixes: 8e8fd0cbd7c5 ("ARM: dts: aspeed: Add Swift BMC machine") Signed-off-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-swift.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts index 25bc0e1bbced..f67fef1ac5e1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts @@ -494,7 +494,7 @@ }; power-supply@68 { - compatible = "ibm,cffps1"; + compatible = "ibm,cffps2"; reg = <0x68>; }; @@ -504,7 +504,7 @@ }; power-supply@69 { - compatible = "ibm,cffps1"; + compatible = "ibm,cffps2"; reg = <0x69>; }; From db3a766d2eeeb4ff4a8ce3a55f0a21c65050dd06 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 4 Sep 2019 10:18:36 -0700 Subject: [PATCH 5/6] ARM; dts: aspeed: mihawk: File should not be executable Remove the executable bit. Fixes: 0a1dcf954ece ("ARM: dts: aspeed: Add Mihawk BMC platform") Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts old mode 100755 new mode 100644 From 89b97c429e2e77d695b5133572ca12ec256a4ea4 Mon Sep 17 00:00:00 2001 From: Oscar A Perez Date: Wed, 1 May 2019 13:26:43 +0000 Subject: [PATCH 6/6] ARM: dts: aspeed-g5: Fixe gpio-ranges upper limit According to the AST2500/AST2520 specs, these SoCs support up to 228 GPIO pins. However, 'gpio-ranges' value in 'aspeed-g5.dtsi' file is currently setting the upper limit to 220 which isn't allowing access to all their GPIOs. The correct upper limit value is 232 (actual number is 228 plus a 4-GPIO hole in GPIOAB). Without this patch, GPIOs AC5 and AC6 do not work correctly on a AST2500 BMC running Linux Kernel v4.19 Fixes: 2039f90d136c ("ARM: dts: aspeed-g5: Add gpio controller to devicetree") Signed-off-by: Oscar A Perez Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index f360b6c565a5..e8feb8b66a2f 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -301,7 +301,7 @@ compatible = "aspeed,ast2500-gpio"; reg = <0x1e780000 0x1000>; interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; + gpio-ranges = <&pinctrl 0 0 232>; clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; #interrupt-cells = <2>;