intel-pinctrl for v5.2-1
Non-critical fixes for Intel Baytrail and Intel Cedarfork. Couple of fixes for all pinctrl-intel based drivers with regard to IRQ handling, i.e. moving PM calls to noirq level to avoid IRQ lose and restore ownership of pins to prevent IRQ masking side effect. The following is an automated git shortlog grouped by driver: baytrail: - Fix potential NULL pointer dereference cedarfork: - Update pin names according to v1.13c intel: - Increase readability of intel_gpio_update_pad_mode() - Retain HOSTSW_OWN for requested gpio pin - move gpio suspend/resume to noirq phase -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAlzGyScACgkQb7wzTHR8 rCjR6w/+OHPEzftvLzlgdOQ8sopxLt/LXoDcDcIufT83VTYdz+QVi0rMPj0fBkDA OWCvvdehJS0VkyOJPw91z8GAxvtjOkqqGoQ8n4V+vzLphjkmNu9R6d243mMH7nCl Trda4MLkmdDtTCQ/iF+tZmzuimKHTLpQfy1Bld0mcNcxdfMLqqe+BD7OtAwIfKr6 LooTVtoqTx+GobmdSWBTaa0+D+nYVsbMwBW/cd+8j/f2MnZ3czhApygCwilAZdU5 etUm2SmCJf2spdkcoxDJ10tih8NH8+dJgmIjU2LTn98pqaSllkT9egfv5tpUq+ag /sRnI1yxi9nmijXMbXl03XUynKxDIlNXcm9hza5EZoLDMAOixwiUSX8ypLTZtSqZ mfC37FMCUKomMvcUtKeya0v8uTJRTLEszS4LuL6q+fopm/sV6nicP3/WIfsAbBwf Kzk8QNZL9CaSRyOxXmnrZvG/CkBYIjVZfJloX7Ia5fZYJBmJ/3U9qfvUqDDJQmn7 EHmhROXRckAjtABa48CyV7BnTQeuhZP6cDFRKZ4AiqHHC8mhJVsSfPq7OUYnET8H V0qix20b5315+VY7I1nYFU7BCJ+gLdef0Hg1znTZFf8Z1poG18feesjujZ3/x2dg fDcS+Il3Z8JXaZT1ljgi+cffzAgWUNpkFn15iBqP3uP6MBbshLU= =tsfB -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.2-1 Non-critical fixes for Intel Baytrail and Intel Cedarfork. Couple of fixes for all pinctrl-intel based drivers with regard to IRQ handling, i.e. moving PM calls to noirq level to avoid IRQ lose and restore ownership of pins to prevent IRQ masking side effect. The following is an automated git shortlog grouped by driver: baytrail: - Fix potential NULL pointer dereference cedarfork: - Update pin names according to v1.13c intel: - Increase readability of intel_gpio_update_pad_mode() - Retain HOSTSW_OWN for requested gpio pin - move gpio suspend/resume to noirq phase
This commit is contained in:
Linus Walleij
Коммит
48f6ae0d75
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@ -1710,6 +1710,8 @@ static int byt_gpio_probe(struct byt_gpio *vg)
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#ifdef CONFIG_PM_SLEEP
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vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
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sizeof(*vg->saved_context), GFP_KERNEL);
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if (!vg->saved_context)
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return -ENOMEM;
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#endif
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ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
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if (ret) {
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@ -91,13 +91,13 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
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PINCTRL_PIN(43, "MEMTRIP_N"),
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PINCTRL_PIN(44, "UART0_RXD"),
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PINCTRL_PIN(45, "UART0_TXD"),
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PINCTRL_PIN(46, "UART1_RXD"),
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PINCTRL_PIN(47, "UART1_TXD"),
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PINCTRL_PIN(46, "GBE_UART_RXD"),
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PINCTRL_PIN(47, "GBE_UART_TXD"),
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/* WEST01 */
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PINCTRL_PIN(48, "GBE_GPIO13"),
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PINCTRL_PIN(49, "AUX_PWR"),
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PINCTRL_PIN(50, "CPU_GP_2"),
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PINCTRL_PIN(51, "CPU_GP_3"),
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PINCTRL_PIN(50, "UART0_RTS"),
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PINCTRL_PIN(51, "UART0_CTS"),
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PINCTRL_PIN(52, "FAN_PWM_0"),
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PINCTRL_PIN(53, "FAN_PWM_1"),
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PINCTRL_PIN(54, "FAN_PWM_2"),
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@ -201,8 +201,8 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
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/* WESTF */
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PINCTRL_PIN(145, "NAC_RMII_CLK"),
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PINCTRL_PIN(146, "NAC_RGMII_CLK"),
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PINCTRL_PIN(147, "NAC_SPARE0"),
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PINCTRL_PIN(148, "NAC_SPARE1"),
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PINCTRL_PIN(147, "NAC_GBE_SMB_CLK_TX_N2S"),
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PINCTRL_PIN(148, "NAC_GBE_SMB_DATA_TX_N2S"),
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PINCTRL_PIN(149, "NAC_SPARE2"),
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PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"),
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PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"),
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@ -219,8 +219,8 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
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PINCTRL_PIN(162, "NAC_NCSI_TXD1"),
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PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"),
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PINCTRL_PIN(164, "NAC_NCSI_OE_N"),
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PINCTRL_PIN(165, "NAC_GBE_SMB_CLK"),
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PINCTRL_PIN(166, "NAC_GBE_SMB_DATA"),
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PINCTRL_PIN(165, "NAC_GBE_SMB_CLK_RX_S2N"),
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PINCTRL_PIN(166, "NAC_GBE_SMB_DATA_RX_S2N"),
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PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"),
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/* EAST2 */
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PINCTRL_PIN(168, "USB_OC0_N"),
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@ -232,7 +232,7 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
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PINCTRL_PIN(174, "GBE_GPIO5"),
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PINCTRL_PIN(175, "GBE_GPIO6"),
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PINCTRL_PIN(176, "GBE_GPIO7"),
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PINCTRL_PIN(177, "GBE_GPIO8"),
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PINCTRL_PIN(177, "SPI_TPM_CS_N"),
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PINCTRL_PIN(178, "GBE_GPIO9"),
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PINCTRL_PIN(179, "GBE_GPIO10"),
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PINCTRL_PIN(180, "GBE_GPIO11"),
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@ -81,6 +81,7 @@ struct intel_pad_context {
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struct intel_community_context {
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u32 *intmask;
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u32 *hostown;
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};
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struct intel_pinctrl_context {
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@ -1284,7 +1285,7 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
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for (i = 0; i < pctrl->ncommunities; i++) {
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struct intel_community *community = &pctrl->communities[i];
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u32 *intmask;
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u32 *intmask, *hostown;
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intmask = devm_kcalloc(pctrl->dev, community->ngpps,
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sizeof(*intmask), GFP_KERNEL);
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@ -1292,6 +1293,13 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
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return -ENOMEM;
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communities[i].intmask = intmask;
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hostown = devm_kcalloc(pctrl->dev, community->ngpps,
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sizeof(*hostown), GFP_KERNEL);
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if (!hostown)
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return -ENOMEM;
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communities[i].hostown = hostown;
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}
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pctrl->context.pads = pads;
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@ -1466,7 +1474,7 @@ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int
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return false;
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}
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int intel_pinctrl_suspend(struct device *dev)
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int intel_pinctrl_suspend_noirq(struct device *dev)
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{
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struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
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struct intel_community_context *communities;
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@ -1501,11 +1509,15 @@ int intel_pinctrl_suspend(struct device *dev)
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base = community->regs + community->ie_offset;
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for (gpp = 0; gpp < community->ngpps; gpp++)
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communities[i].intmask[gpp] = readl(base + gpp * 4);
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base = community->regs + community->hostown_offset;
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for (gpp = 0; gpp < community->ngpps; gpp++)
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communities[i].hostown[gpp] = readl(base + gpp * 4);
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
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EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
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static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
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{
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@ -1527,7 +1539,32 @@ static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
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}
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}
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int intel_pinctrl_resume(struct device *dev)
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static u32
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intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size)
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{
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u32 requested = 0;
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unsigned int i;
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for (i = 0; i < size; i++)
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if (gpiochip_is_requested(chip, base + i))
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requested |= BIT(i);
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return requested;
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}
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static u32
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intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value)
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{
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u32 curr, updated;
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curr = readl(hostown);
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updated = (curr & ~mask) | (value & mask);
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writel(updated, hostown);
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return curr;
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}
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int intel_pinctrl_resume_noirq(struct device *dev)
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{
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struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
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const struct intel_community_context *communities;
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@ -1585,11 +1622,30 @@ int intel_pinctrl_resume(struct device *dev)
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dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
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readl(base + gpp * 4));
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}
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base = community->regs + community->hostown_offset;
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for (gpp = 0; gpp < community->ngpps; gpp++) {
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const struct intel_padgroup *padgrp = &community->gpps[gpp];
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u32 requested = 0, value = 0;
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u32 saved = communities[i].hostown[gpp];
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if (padgrp->gpio_base < 0)
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continue;
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requested = intel_gpio_is_requested(&pctrl->chip,
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padgrp->gpio_base, padgrp->size);
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value = intel_gpio_update_pad_mode(base + gpp * 4,
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requested, saved);
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if ((value ^ saved) & requested) {
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dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n",
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i, gpp, value, saved);
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}
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}
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
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EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
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#endif
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MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
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@ -177,13 +177,14 @@ int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
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int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
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#ifdef CONFIG_PM_SLEEP
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int intel_pinctrl_suspend(struct device *dev);
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int intel_pinctrl_resume(struct device *dev);
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int intel_pinctrl_suspend_noirq(struct device *dev);
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int intel_pinctrl_resume_noirq(struct device *dev);
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#endif
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#define INTEL_PINCTRL_PM_OPS(_name) \
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const struct dev_pm_ops _name = { \
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SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, intel_pinctrl_resume) \
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#define INTEL_PINCTRL_PM_OPS(_name) \
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const struct dev_pm_ops _name = { \
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \
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intel_pinctrl_resume_noirq) \
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}
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#endif /* PINCTRL_INTEL_H */
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