scsi: ufshcd: remove unused quirks
Remove various quirks that don't have users, as well as the dead code keyed off them. Link: https://lore.kernel.org/r/20200221140812.476338-2-hch@lst.de Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Christoph Hellwig
Martin K. Petersen
Родитель
4cbca7ea9e
Коммит
492001990f
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@ -645,11 +645,7 @@ static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
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*/
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static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
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{
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if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
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ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
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else
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ufshcd_writel(hba, ~(1 << pos),
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REG_UTP_TRANSFER_REQ_LIST_CLEAR);
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ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
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}
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/**
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@ -659,10 +655,7 @@ static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
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*/
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static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
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{
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if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
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ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
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else
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ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
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ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
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}
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/**
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@ -2101,13 +2094,8 @@ static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
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return sg_segments;
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if (sg_segments) {
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if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
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lrbp->utr_descriptor_ptr->prd_table_length =
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cpu_to_le16((u16)(sg_segments *
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sizeof(struct ufshcd_sg_entry)));
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else
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lrbp->utr_descriptor_ptr->prd_table_length =
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cpu_to_le16((u16) (sg_segments));
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lrbp->utr_descriptor_ptr->prd_table_length =
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cpu_to_le16((u16)sg_segments);
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prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
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@ -3436,21 +3424,11 @@ static void ufshcd_host_memory_configure(struct ufs_hba *hba)
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cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
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/* Response upiu and prdt offset should be in double words */
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if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
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utrdlp[i].response_upiu_offset =
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cpu_to_le16(response_offset);
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utrdlp[i].prd_table_offset =
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cpu_to_le16(prdt_offset);
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utrdlp[i].response_upiu_length =
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cpu_to_le16(ALIGNED_UPIU_SIZE);
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} else {
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utrdlp[i].response_upiu_offset =
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cpu_to_le16((response_offset >> 2));
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utrdlp[i].prd_table_offset =
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cpu_to_le16((prdt_offset >> 2));
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utrdlp[i].response_upiu_length =
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cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
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}
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utrdlp[i].response_upiu_offset =
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cpu_to_le16(response_offset >> 2);
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utrdlp[i].prd_table_offset = cpu_to_le16(prdt_offset >> 2);
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utrdlp[i].response_upiu_length =
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cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
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hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
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hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
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@ -3493,52 +3471,6 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
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"dme-link-startup: error code %d\n", ret);
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return ret;
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}
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/**
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* ufshcd_dme_reset - UIC command for DME_RESET
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* @hba: per adapter instance
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*
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* DME_RESET command is issued in order to reset UniPro stack.
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* This function now deal with cold reset.
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*
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* Returns 0 on success, non-zero value on failure
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*/
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static int ufshcd_dme_reset(struct ufs_hba *hba)
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{
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struct uic_command uic_cmd = {0};
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int ret;
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uic_cmd.command = UIC_CMD_DME_RESET;
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ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
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if (ret)
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dev_err(hba->dev,
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"dme-reset: error code %d\n", ret);
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return ret;
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}
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/**
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* ufshcd_dme_enable - UIC command for DME_ENABLE
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* @hba: per adapter instance
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*
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* DME_ENABLE command is issued in order to enable UniPro stack.
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*
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* Returns 0 on success, non-zero value on failure
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*/
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static int ufshcd_dme_enable(struct ufs_hba *hba)
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{
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struct uic_command uic_cmd = {0};
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int ret;
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uic_cmd.command = UIC_CMD_DME_ENABLE;
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ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
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if (ret)
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dev_err(hba->dev,
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"dme-reset: error code %d\n", ret);
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return ret;
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}
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static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
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{
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@ -4250,7 +4182,7 @@ static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
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}
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/**
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* ufshcd_hba_execute_hce - initialize the controller
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* ufshcd_hba_enable - initialize the controller
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* @hba: per adapter instance
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*
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* The controller resets itself and controller firmware initialization
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@ -4259,7 +4191,7 @@ static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
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*
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* Returns 0 on success, non-zero value on failure
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*/
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static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
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int ufshcd_hba_enable(struct ufs_hba *hba)
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{
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int retry;
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@ -4307,32 +4239,6 @@ static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
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return 0;
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}
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int ufshcd_hba_enable(struct ufs_hba *hba)
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{
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int ret;
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if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
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ufshcd_set_link_off(hba);
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ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
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/* enable UIC related interrupts */
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ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
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ret = ufshcd_dme_reset(hba);
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if (!ret) {
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ret = ufshcd_dme_enable(hba);
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if (!ret)
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ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
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if (ret)
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dev_err(hba->dev,
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"Host controller enable failed with non-hce\n");
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}
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} else {
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ret = ufshcd_hba_execute_hce(hba);
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}
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return ret;
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}
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EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
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static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
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@ -4909,8 +4815,7 @@ static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
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* false interrupt if device completes another request after resetting
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* aggregation and before reading the DB.
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*/
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if (ufshcd_is_intr_aggr_allowed(hba) &&
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!(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
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if (ufshcd_is_intr_aggr_allowed(hba))
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ufshcd_reset_intr_aggr(hba);
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tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
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@ -613,28 +613,6 @@ struct ufs_hba {
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*/
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#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION 0x20
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/*
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* This quirk needs to be enabled if the host contoller regards
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* resolution of the values of PRDTO and PRDTL in UTRD as byte.
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*/
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#define UFSHCD_QUIRK_PRDT_BYTE_GRAN 0x80
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/*
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* Clear handling for transfer/task request list is just opposite.
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*/
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#define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR 0x100
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/*
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* This quirk needs to be enabled if host controller doesn't allow
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* that the interrupt aggregation timer and counter are reset by s/w.
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*/
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#define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR 0x200
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/*
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* This quirks needs to be enabled if host controller cannot be
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* enabled via HCE register.
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*/
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#define UFSHCI_QUIRK_BROKEN_HCE 0x400
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unsigned int quirks; /* Deviations from standard UFSHCI spec. */
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/* Device deviations from standard UFS device spec. */
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