RDMA/hns: Refactor hns_roce_v2_poll_one()
Encapsulate the process of obtaining the current QP and filling WC as functions, also merge some duplicate code. Link: https://lore.kernel.org/r/1616815294-13434-2-git-send-email-liweihang@huawei.com Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Weihang Li
Jason Gunthorpe
Родитель
d907294b27
Коммит
4940b0ab45
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@ -3303,8 +3303,8 @@ static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
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}
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static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
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struct hns_roce_qp **cur_qp,
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struct ib_wc *wc)
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struct hns_roce_qp *qp,
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struct ib_wc *wc)
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{
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struct hns_roce_rinl_sge *sge_list;
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u32 wr_num, wr_cnt, sge_num;
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@ -3313,11 +3313,11 @@ static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
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wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
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V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
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wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
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wr_cnt = wr_num & (qp->rq.wqe_cnt - 1);
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sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
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sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
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wqe_buf = hns_roce_get_recv_wqe(*cur_qp, wr_cnt);
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sge_list = qp->rq_inl_buf.wqe_list[wr_cnt].sg_list;
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sge_num = qp->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
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wqe_buf = hns_roce_get_recv_wqe(qp, wr_cnt);
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data_len = wc->byte_len;
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for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
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@ -3451,21 +3451,205 @@ static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
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init_flush_work(hr_dev, qp);
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}
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static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe,
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struct hns_roce_qp **cur_qp)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
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struct hns_roce_qp *hr_qp = *cur_qp;
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u32 qpn;
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qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
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V2_CQE_BYTE_16_LCL_QPN_S) &
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HNS_ROCE_V2_CQE_QPN_MASK;
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if (!hr_qp || qpn != hr_qp->qpn) {
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hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
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if (unlikely(!hr_qp)) {
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ibdev_err(&hr_dev->ib_dev,
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"CQ %06lx with entry for unknown QPN %06x\n",
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hr_cq->cqn, qpn);
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return -EINVAL;
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}
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*cur_qp = hr_qp;
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}
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return 0;
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}
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/*
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* mapped-value = 1 + real-value
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* The ib wc opcode's real value is start from 0, In order to distinguish
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* between initialized and uninitialized map values, we plus 1 to the actual
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* value when defining the mapping, so that the validity can be identified by
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* checking whether the mapped value is greater than 0.
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*/
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#define HR_WC_OP_MAP(hr_key, ib_key) \
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[HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key
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static const u32 wc_send_op_map[] = {
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HR_WC_OP_MAP(SEND, SEND),
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HR_WC_OP_MAP(SEND_WITH_INV, SEND),
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HR_WC_OP_MAP(SEND_WITH_IMM, SEND),
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HR_WC_OP_MAP(RDMA_READ, RDMA_READ),
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HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE),
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HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE),
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HR_WC_OP_MAP(LOCAL_INV, LOCAL_INV),
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HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP),
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HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD),
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HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP),
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HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD),
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HR_WC_OP_MAP(FAST_REG_PMR, REG_MR),
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HR_WC_OP_MAP(BIND_MW, REG_MR),
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};
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static int to_ib_wc_send_op(u32 hr_opcode)
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{
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if (hr_opcode >= ARRAY_SIZE(wc_send_op_map))
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return -EINVAL;
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return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 :
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-EINVAL;
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}
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static const u32 wc_recv_op_map[] = {
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HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM),
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HR_WC_OP_MAP(SEND, RECV),
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HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM),
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HR_WC_OP_MAP(SEND_WITH_INV, RECV),
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};
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static int to_ib_wc_recv_op(u32 hr_opcode)
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{
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if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map))
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return -EINVAL;
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return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 :
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-EINVAL;
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}
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static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
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{
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u32 hr_opcode;
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int ib_opcode;
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wc->wc_flags = 0;
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hr_opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
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V2_CQE_BYTE_4_OPCODE_S) & 0x1f;
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switch (hr_opcode) {
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case HNS_ROCE_V2_WQE_OP_RDMA_READ:
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wc->byte_len = le32_to_cpu(cqe->byte_cnt);
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break;
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case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
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case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
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wc->wc_flags |= IB_WC_WITH_IMM;
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break;
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case HNS_ROCE_V2_WQE_OP_LOCAL_INV:
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wc->wc_flags |= IB_WC_WITH_INVALIDATE;
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break;
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case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
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case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
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case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
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case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
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wc->byte_len = 8;
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break;
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default:
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break;
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}
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ib_opcode = to_ib_wc_send_op(hr_opcode);
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if (ib_opcode < 0)
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wc->status = IB_WC_GENERAL_ERR;
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else
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wc->opcode = ib_opcode;
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}
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static inline bool is_rq_inl_enabled(struct ib_wc *wc, u32 hr_opcode,
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struct hns_roce_v2_cqe *cqe)
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{
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return wc->qp->qp_type != IB_QPT_UD &&
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wc->qp->qp_type != IB_QPT_GSI &&
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(hr_opcode == HNS_ROCE_V2_OPCODE_SEND ||
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hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
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hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
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roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S);
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}
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static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
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{
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struct hns_roce_qp *qp = to_hr_qp(wc->qp);
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u32 hr_opcode;
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int ib_opcode;
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int ret;
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wc->byte_len = le32_to_cpu(cqe->byte_cnt);
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hr_opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
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V2_CQE_BYTE_4_OPCODE_S) & 0x1f;
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switch (hr_opcode) {
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case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
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case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
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wc->wc_flags = IB_WC_WITH_IMM;
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wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata));
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break;
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case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
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wc->wc_flags = IB_WC_WITH_INVALIDATE;
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wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
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break;
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default:
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wc->wc_flags = 0;
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}
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ib_opcode = to_ib_wc_recv_op(hr_opcode);
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if (ib_opcode < 0)
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wc->status = IB_WC_GENERAL_ERR;
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else
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wc->opcode = ib_opcode;
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if (is_rq_inl_enabled(wc, hr_opcode, cqe)) {
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ret = hns_roce_handle_recv_inl_wqe(cqe, qp, wc);
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if (unlikely(ret))
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return ret;
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}
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wc->sl = roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
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V2_CQE_BYTE_32_SL_S);
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wc->src_qp = roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_RMT_QPN_M,
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V2_CQE_BYTE_32_RMT_QPN_S);
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wc->slid = 0;
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wc->wc_flags |= roce_get_bit(cqe->byte_32, V2_CQE_BYTE_32_GRH_S) ?
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IB_WC_GRH : 0;
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wc->port_num = roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_PORTN_M,
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V2_CQE_BYTE_32_PORTN_S);
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wc->pkey_index = 0;
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if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
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wc->vlan_id = roce_get_field(cqe->byte_28, V2_CQE_BYTE_28_VID_M,
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V2_CQE_BYTE_28_VID_S);
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wc->wc_flags |= IB_WC_WITH_VLAN;
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} else {
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wc->vlan_id = 0xffff;
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}
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wc->network_hdr_type = roce_get_field(cqe->byte_28,
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V2_CQE_BYTE_28_PORT_TYPE_M,
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V2_CQE_BYTE_28_PORT_TYPE_S);
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return 0;
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}
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static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
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struct hns_roce_qp **cur_qp, struct ib_wc *wc)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
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struct hns_roce_qp *qp = *cur_qp;
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struct hns_roce_srq *srq = NULL;
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struct hns_roce_v2_cqe *cqe;
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struct hns_roce_qp *hr_qp;
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struct hns_roce_wq *wq;
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int is_send;
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u16 wqe_ctr;
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u32 opcode;
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u32 qpn;
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u16 wqe_idx;
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int ret;
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/* Find cqe according to consumer index */
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cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
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if (!cqe)
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return -EAGAIN;
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@ -3474,189 +3658,50 @@ static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
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/* Memory barrier */
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rmb();
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/* 0->SQ, 1->RQ */
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is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
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ret = get_cur_qp(hr_cq, cqe, &qp);
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if (ret)
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return ret;
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qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
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V2_CQE_BYTE_16_LCL_QPN_S);
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if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
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hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
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if (unlikely(!hr_qp)) {
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ibdev_err(&hr_dev->ib_dev,
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"CQ %06lx with entry for unknown QPN %06x\n",
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hr_cq->cqn, qpn & HNS_ROCE_V2_CQE_QPN_MASK);
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return -EINVAL;
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}
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*cur_qp = hr_qp;
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}
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wc->qp = &(*cur_qp)->ibqp;
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wc->qp = &qp->ibqp;
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wc->vendor_err = 0;
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wqe_idx = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
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V2_CQE_BYTE_4_WQE_INDX_S);
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is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
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if (is_send) {
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wq = &(*cur_qp)->sq;
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if ((*cur_qp)->sq_signal_bits) {
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/*
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* If sg_signal_bit is 1,
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* firstly tail pointer updated to wqe
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* which current cqe correspond to
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*/
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wqe_ctr = (u16)roce_get_field(cqe->byte_4,
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V2_CQE_BYTE_4_WQE_INDX_M,
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V2_CQE_BYTE_4_WQE_INDX_S);
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wq->tail += (wqe_ctr - (u16)wq->tail) &
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wq = &qp->sq;
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/* If sg_signal_bit is set, tail pointer will be updated to
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* the WQE corresponding to the current CQE.
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*/
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if (qp->sq_signal_bits)
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wq->tail += (wqe_idx - (u16)wq->tail) &
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(wq->wqe_cnt - 1);
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wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
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++wq->tail;
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fill_send_wc(wc, cqe);
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} else {
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if (qp->ibqp.srq) {
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srq = to_hr_srq(qp->ibqp.srq);
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wc->wr_id = srq->wrid[wqe_idx];
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hns_roce_free_srq_wqe(srq, wqe_idx);
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} else {
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wq = &qp->rq;
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wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
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++wq->tail;
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}
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wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
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++wq->tail;
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} else if ((*cur_qp)->ibqp.srq) {
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srq = to_hr_srq((*cur_qp)->ibqp.srq);
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wqe_ctr = (u16)roce_get_field(cqe->byte_4,
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V2_CQE_BYTE_4_WQE_INDX_M,
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V2_CQE_BYTE_4_WQE_INDX_S);
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wc->wr_id = srq->wrid[wqe_ctr];
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hns_roce_free_srq_wqe(srq, wqe_ctr);
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} else {
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/* Update tail pointer, record wr_id */
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wq = &(*cur_qp)->rq;
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wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
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++wq->tail;
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ret = fill_recv_wc(wc, cqe);
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}
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get_cqe_status(hr_dev, *cur_qp, hr_cq, cqe, wc);
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get_cqe_status(hr_dev, qp, hr_cq, cqe, wc);
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if (unlikely(wc->status != IB_WC_SUCCESS))
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return 0;
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if (is_send) {
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wc->wc_flags = 0;
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/* SQ corresponding to CQE */
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switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
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V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
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case HNS_ROCE_V2_WQE_OP_SEND:
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wc->opcode = IB_WC_SEND;
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break;
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case HNS_ROCE_V2_WQE_OP_SEND_WITH_INV:
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wc->opcode = IB_WC_SEND;
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break;
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case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
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wc->opcode = IB_WC_SEND;
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wc->wc_flags |= IB_WC_WITH_IMM;
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break;
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case HNS_ROCE_V2_WQE_OP_RDMA_READ:
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wc->opcode = IB_WC_RDMA_READ;
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wc->byte_len = le32_to_cpu(cqe->byte_cnt);
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break;
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case HNS_ROCE_V2_WQE_OP_RDMA_WRITE:
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wc->opcode = IB_WC_RDMA_WRITE;
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break;
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case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
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wc->opcode = IB_WC_RDMA_WRITE;
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wc->wc_flags |= IB_WC_WITH_IMM;
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break;
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case HNS_ROCE_V2_WQE_OP_LOCAL_INV:
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wc->opcode = IB_WC_LOCAL_INV;
|
||||
wc->wc_flags |= IB_WC_WITH_INVALIDATE;
|
||||
break;
|
||||
case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
|
||||
wc->opcode = IB_WC_COMP_SWAP;
|
||||
wc->byte_len = 8;
|
||||
break;
|
||||
case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
|
||||
wc->opcode = IB_WC_FETCH_ADD;
|
||||
wc->byte_len = 8;
|
||||
break;
|
||||
case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
|
||||
wc->opcode = IB_WC_MASKED_COMP_SWAP;
|
||||
wc->byte_len = 8;
|
||||
break;
|
||||
case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
|
||||
wc->opcode = IB_WC_MASKED_FETCH_ADD;
|
||||
wc->byte_len = 8;
|
||||
break;
|
||||
case HNS_ROCE_V2_WQE_OP_FAST_REG_PMR:
|
||||
wc->opcode = IB_WC_REG_MR;
|
||||
break;
|
||||
case HNS_ROCE_V2_WQE_OP_BIND_MW:
|
||||
wc->opcode = IB_WC_REG_MR;
|
||||
break;
|
||||
default:
|
||||
wc->status = IB_WC_GENERAL_ERR;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/* RQ correspond to CQE */
|
||||
wc->byte_len = le32_to_cpu(cqe->byte_cnt);
|
||||
|
||||
opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
|
||||
V2_CQE_BYTE_4_OPCODE_S);
|
||||
switch (opcode & 0x1f) {
|
||||
case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
|
||||
wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
|
||||
wc->wc_flags = IB_WC_WITH_IMM;
|
||||
wc->ex.imm_data =
|
||||
cpu_to_be32(le32_to_cpu(cqe->immtdata));
|
||||
break;
|
||||
case HNS_ROCE_V2_OPCODE_SEND:
|
||||
wc->opcode = IB_WC_RECV;
|
||||
wc->wc_flags = 0;
|
||||
break;
|
||||
case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
|
||||
wc->opcode = IB_WC_RECV;
|
||||
wc->wc_flags = IB_WC_WITH_IMM;
|
||||
wc->ex.imm_data =
|
||||
cpu_to_be32(le32_to_cpu(cqe->immtdata));
|
||||
break;
|
||||
case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
|
||||
wc->opcode = IB_WC_RECV;
|
||||
wc->wc_flags = IB_WC_WITH_INVALIDATE;
|
||||
wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
|
||||
break;
|
||||
default:
|
||||
wc->status = IB_WC_GENERAL_ERR;
|
||||
break;
|
||||
}
|
||||
|
||||
if ((wc->qp->qp_type == IB_QPT_RC ||
|
||||
wc->qp->qp_type == IB_QPT_UC) &&
|
||||
(opcode == HNS_ROCE_V2_OPCODE_SEND ||
|
||||
opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
|
||||
opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
|
||||
(roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
|
||||
ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
|
||||
if (unlikely(ret))
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
|
||||
V2_CQE_BYTE_32_SL_S);
|
||||
wc->src_qp = (u8)roce_get_field(cqe->byte_32,
|
||||
V2_CQE_BYTE_32_RMT_QPN_M,
|
||||
V2_CQE_BYTE_32_RMT_QPN_S);
|
||||
wc->slid = 0;
|
||||
wc->wc_flags |= (roce_get_bit(cqe->byte_32,
|
||||
V2_CQE_BYTE_32_GRH_S) ?
|
||||
IB_WC_GRH : 0);
|
||||
wc->port_num = roce_get_field(cqe->byte_32,
|
||||
V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
|
||||
wc->pkey_index = 0;
|
||||
|
||||
if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
|
||||
wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
|
||||
V2_CQE_BYTE_28_VID_M,
|
||||
V2_CQE_BYTE_28_VID_S);
|
||||
wc->wc_flags |= IB_WC_WITH_VLAN;
|
||||
} else {
|
||||
wc->vlan_id = 0xffff;
|
||||
}
|
||||
|
||||
wc->network_hdr_type = roce_get_field(cqe->byte_28,
|
||||
V2_CQE_BYTE_28_PORT_TYPE_M,
|
||||
V2_CQE_BYTE_28_PORT_TYPE_S);
|
||||
}
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче