ARM: 7517/1: integrator: initial device tree support
This is initial device tree support for the ARM Integrator family, we create a very basic device tree, #ifdef out the non-DT machines when compiling for device tree. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Linus Walleij
Russell King
Родитель
dc81df520b
Коммит
4980f9bc2c
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@ -1,3 +1,15 @@
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ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform)
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-----------------------------------------------------------------------------
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ARM's oldest Linux-supported platform with connectors for different core
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tiles of ARMv4, ARMv5 and ARMv6 type.
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Required properties (in root node):
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compatible = "arm,integrator-ap"; /* Application Platform */
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compatible = "arm,integrator-cp"; /* Compact Platform */
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FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
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ARM Versatile Application and Platform Baseboards
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-------------------------------------------------
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ARM's development hardware platform with connectors for customizable
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@ -0,0 +1,33 @@
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/*
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* SoC core Device Tree for the ARM Integrator platforms
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*/
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/include/ "skeleton.dtsi"
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/ {
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timer@13000000 {
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reg = <0x13000000 0x100>;
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interrupt-parent = <&pic>;
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interrupts = <5>;
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};
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timer@13000100 {
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reg = <0x13000100 0x100>;
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interrupt-parent = <&pic>;
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interrupts = <6>;
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};
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timer@13000200 {
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reg = <0x13000200 0x100>;
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interrupt-parent = <&pic>;
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interrupts = <7>;
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};
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pic@14000000 {
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compatible = "arm,versatile-fpga-irq";
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0x14000000 0x100>;
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clear-mask = <0xffffffff>;
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};
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};
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@ -0,0 +1,36 @@
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/*
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* Device Tree for the ARM Integrator/AP platform
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*/
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/dts-v1/;
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/include/ "integrator.dtsi"
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/ {
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model = "ARM Integrator/AP";
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compatible = "arm,integrator-ap";
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aliases {
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arm,timer-primary = &timer2;
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arm,timer-secondary = &timer1;
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};
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chosen {
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bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
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};
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timer0: timer@13000000 {
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compatible = "arm,integrator-timer";
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};
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timer1: timer@13000100 {
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compatible = "arm,integrator-timer";
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};
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timer2: timer@13000200 {
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compatible = "arm,integrator-timer";
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};
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pic: pic@14000000 {
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valid-mask = <0x003fffff>;
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};
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};
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@ -0,0 +1,54 @@
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/*
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* Device Tree for the ARM Integrator/CP platform
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*/
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/dts-v1/;
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/include/ "integrator.dtsi"
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/ {
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model = "ARM Integrator/CP";
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compatible = "arm,integrator-cp";
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aliases {
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arm,timer-primary = &timer2;
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arm,timer-secondary = &timer1;
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};
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chosen {
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bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
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};
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timer0: timer@13000000 {
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compatible = "arm,sp804", "arm,primecell";
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};
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timer1: timer@13000100 {
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compatible = "arm,sp804", "arm,primecell";
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};
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timer2: timer@13000200 {
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compatible = "arm,sp804", "arm,primecell";
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};
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pic: pic@14000000 {
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valid-mask = <0x1fc003ff>;
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};
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cic: cic@10000040 {
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compatible = "arm,versatile-fpga-irq";
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0x10000040 0x100>;
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clear-mask = <0xffffffff>;
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valid-mask = <0x00000007>;
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};
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sic: sic@ca000000 {
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compatible = "arm,versatile-fpga-irq";
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0xca000000 0x100>;
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clear-mask = <0x00000fff>;
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valid-mask = <0x00000fff>;
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};
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};
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@ -34,6 +34,8 @@
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#include <linux/mtd/physmap.h>
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#include <linux/clk.h>
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#include <linux/platform_data/clk-integrator.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <video/vga.h>
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#include <mach/hardware.h>
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@ -161,23 +163,6 @@ static void __init ap_map_io(void)
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vga_base = PCI_MEMORY_VADDR;
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}
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#define INTEGRATOR_SC_VALID_INT 0x003fffff
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static void __init ap_init_irq(void)
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{
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/* Disable all interrupts initially. */
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/* Do the core module ones */
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writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
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/* do the header card stuff next */
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writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
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fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
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-1, INTEGRATOR_SC_VALID_INT, NULL);
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integrator_clk_init(false);
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}
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#ifdef CONFIG_PM
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static unsigned long ic_irq_enable;
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@ -330,9 +315,9 @@ static u32 notrace integrator_read_sched_clock(void)
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return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
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}
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static void integrator_clocksource_init(unsigned long inrate)
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static void integrator_clocksource_init(unsigned long inrate,
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void __iomem *base)
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{
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void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
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u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
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unsigned long rate = inrate;
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@ -349,7 +334,7 @@ static void integrator_clocksource_init(unsigned long inrate)
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setup_sched_clock(integrator_read_sched_clock, 16, rate);
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}
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static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
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static void __iomem * clkevt_base;
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/*
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* IRQ handler for the timer
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@ -421,11 +406,13 @@ static struct irqaction integrator_timer_irq = {
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.dev_id = &integrator_clockevent,
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};
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static void integrator_clockevent_init(unsigned long inrate)
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static void integrator_clockevent_init(unsigned long inrate,
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void __iomem *base, int irq)
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{
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unsigned long rate = inrate;
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unsigned int ctrl = 0;
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clkevt_base = base;
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/* Calculate and program a divisor */
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if (rate > 0x100000 * HZ) {
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rate /= 256;
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@ -437,7 +424,7 @@ static void integrator_clockevent_init(unsigned long inrate)
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timer_reload = rate / HZ;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
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setup_irq(irq, &integrator_timer_irq);
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clockevents_config_and_register(&integrator_clockevent,
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rate,
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1,
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@ -448,9 +435,91 @@ void __init ap_init_early(void)
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{
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}
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#ifdef CONFIG_OF
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static void __init ap_init_timer_of(void)
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{
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struct device_node *node;
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const char *path;
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void __iomem *base;
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int err;
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int irq;
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struct clk *clk;
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unsigned long rate;
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clk = clk_get_sys("ap_timer", NULL);
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BUG_ON(IS_ERR(clk));
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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err = of_property_read_string(of_aliases,
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"arm,timer-primary", &path);
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if (WARN_ON(err))
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return;
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node = of_find_node_by_path(path);
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base = of_iomap(node, 0);
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if (WARN_ON(!base))
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return;
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writel(0, base + TIMER_CTRL);
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integrator_clocksource_init(rate, base);
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err = of_property_read_string(of_aliases,
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"arm,timer-secondary", &path);
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if (WARN_ON(err))
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return;
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node = of_find_node_by_path(path);
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base = of_iomap(node, 0);
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if (WARN_ON(!base))
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return;
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irq = irq_of_parse_and_map(node, 0);
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writel(0, base + TIMER_CTRL);
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integrator_clockevent_init(rate, base, irq);
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}
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static struct sys_timer ap_of_timer = {
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.init = ap_init_timer_of,
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};
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static const struct of_device_id fpga_irq_of_match[] __initconst = {
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{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
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{ /* Sentinel */ }
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};
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static void __init ap_init_irq_of(void)
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{
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/* disable core module IRQs */
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writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
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of_irq_init(fpga_irq_of_match);
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integrator_clk_init(false);
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}
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static const char * ap_dt_board_compat[] = {
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"arm,integrator-ap",
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NULL,
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};
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DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
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.reserve = integrator_reserve,
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.map_io = ap_map_io,
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.nr_irqs = NR_IRQS_INTEGRATOR_AP,
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.init_early = ap_init_early,
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.init_irq = ap_init_irq_of,
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.handle_irq = fpga_handle_irq,
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.timer = &ap_of_timer,
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.init_machine = ap_init,
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.restart = integrator_restart,
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.dt_compat = ap_dt_board_compat,
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MACHINE_END
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#endif
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#ifdef CONFIG_ATAGS
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/*
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* Set up timer(s).
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* This is where non-devicetree initialization code is collected and stashed
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* for eventual deletion.
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*/
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static void __init ap_init_timer(void)
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{
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struct clk *clk;
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@ -465,14 +534,32 @@ static void __init ap_init_timer(void)
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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integrator_clocksource_init(rate);
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integrator_clockevent_init(rate);
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integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
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integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
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IRQ_TIMERINT1);
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}
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static struct sys_timer ap_timer = {
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.init = ap_init_timer,
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};
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#define INTEGRATOR_SC_VALID_INT 0x003fffff
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static void __init ap_init_irq(void)
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{
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/* Disable all interrupts initially. */
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/* Do the core module ones */
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writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
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/* do the header card stuff next */
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writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
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fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
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-1, INTEGRATOR_SC_VALID_INT, NULL);
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integrator_clk_init(false);
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}
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MACHINE_START(INTEGRATOR, "ARM-Integrator")
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/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
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.atag_offset = 0x100,
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@ -486,3 +573,5 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
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.init_machine = ap_init,
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.restart = integrator_restart,
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MACHINE_END
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#endif
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@ -23,6 +23,8 @@
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#include <linux/gfp.h>
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#include <linux/mtd/physmap.h>
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#include <linux/platform_data/clk-integrator.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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@ -53,10 +55,6 @@
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#define INTCP_PA_CLCD_BASE 0xc0000000
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#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
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#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
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#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
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#define INTCP_ETH_SIZE 0x10
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#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
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@ -143,37 +141,6 @@ static void __init intcp_map_io(void)
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iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
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}
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static void __init intcp_init_irq(void)
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{
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u32 pic_mask, cic_mask, sic_mask;
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/* These masks are for the HW IRQ registers */
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pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
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pic_mask |= (~((~0u) << (29 - 22))) << 22;
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cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
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sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
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/*
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* Disable all interrupt sources
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*/
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writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
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writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
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writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
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writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
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writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
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writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
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fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
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-1, pic_mask, NULL);
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fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
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-1, cic_mask, NULL);
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fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
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IRQ_CP_CPPLDINT, sic_mask, NULL);
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integrator_clk_init(true);
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}
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/*
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* Flash handling.
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*/
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@ -356,17 +323,116 @@ static void __init intcp_init_early(void)
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#endif
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}
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static void __init intcp_init(void)
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static void __init intcp_timer_init_of(void)
|
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{
|
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int i;
|
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struct device_node *node;
|
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const char *path;
|
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void __iomem *base;
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int err;
|
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int irq;
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platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
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err = of_property_read_string(of_aliases,
|
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"arm,timer-primary", &path);
|
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if (WARN_ON(err))
|
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return;
|
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node = of_find_node_by_path(path);
|
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base = of_iomap(node, 0);
|
||||
if (WARN_ON(!base))
|
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return;
|
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writel(0, base + TIMER_CTRL);
|
||||
sp804_clocksource_init(base, node->name);
|
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|
||||
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
|
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struct amba_device *d = amba_devs[i];
|
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amba_device_register(d, &iomem_resource);
|
||||
}
|
||||
integrator_init(true);
|
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err = of_property_read_string(of_aliases,
|
||||
"arm,timer-secondary", &path);
|
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if (WARN_ON(err))
|
||||
return;
|
||||
node = of_find_node_by_path(path);
|
||||
base = of_iomap(node, 0);
|
||||
if (WARN_ON(!base))
|
||||
return;
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
writel(0, base + TIMER_CTRL);
|
||||
sp804_clockevents_init(base, irq, node->name);
|
||||
}
|
||||
|
||||
static struct sys_timer cp_of_timer = {
|
||||
.init = intcp_timer_init_of,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
||||
static const struct of_device_id fpga_irq_of_match[] __initconst = {
|
||||
{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
|
||||
static void __init intcp_init_irq_of(void)
|
||||
{
|
||||
of_irq_init(fpga_irq_of_match);
|
||||
integrator_clk_init(true);
|
||||
}
|
||||
|
||||
static const char * intcp_dt_board_compat[] = {
|
||||
"arm,integrator-cp",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
|
||||
.reserve = integrator_reserve,
|
||||
.map_io = intcp_map_io,
|
||||
.nr_irqs = NR_IRQS_INTEGRATOR_CP,
|
||||
.init_early = intcp_init_early,
|
||||
.init_irq = intcp_init_irq_of,
|
||||
.handle_irq = fpga_handle_irq,
|
||||
.timer = &cp_of_timer,
|
||||
.init_machine = intcp_init,
|
||||
.restart = integrator_restart,
|
||||
.dt_compat = intcp_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ATAGS
|
||||
|
||||
/*
|
||||
* This is where non-devicetree initialization code is collected and stashed
|
||||
* for eventual deletion.
|
||||
*/
|
||||
|
||||
#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
|
||||
#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
|
||||
#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
|
||||
|
||||
static void __init intcp_init_irq(void)
|
||||
{
|
||||
u32 pic_mask, cic_mask, sic_mask;
|
||||
|
||||
/* These masks are for the HW IRQ registers */
|
||||
pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
|
||||
pic_mask |= (~((~0u) << (29 - 22))) << 22;
|
||||
cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
|
||||
sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
|
||||
|
||||
/*
|
||||
* Disable all interrupt sources
|
||||
*/
|
||||
writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
|
||||
writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
|
||||
writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
|
||||
writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
|
||||
writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
|
||||
writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
|
||||
|
||||
fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
|
||||
-1, pic_mask, NULL);
|
||||
|
||||
fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
|
||||
-1, cic_mask, NULL);
|
||||
|
||||
fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
|
||||
IRQ_CP_CPPLDINT, sic_mask, NULL);
|
||||
|
||||
integrator_clk_init(true);
|
||||
}
|
||||
|
||||
#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
|
||||
|
|
@ -400,3 +466,5 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
|
|||
.init_machine = intcp_init,
|
||||
.restart = integrator_restart,
|
||||
MACHINE_END
|
||||
|
||||
#endif
|
||||
|
|
|
|||
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