drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as well
This way we save passing it through the different functions. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -57,6 +57,8 @@
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struct amdgpu_pte_update_params {
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/* amdgpu device we do this update for */
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struct amdgpu_device *adev;
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/* optional amdgpu_vm we do this update for */
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struct amdgpu_vm *vm;
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/* address where to copy page table entries from */
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uint64_t src;
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/* indirect buffer to fill with commands */
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@ -804,7 +806,6 @@ error_free:
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* Update the page tables in the range @start - @end.
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*/
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static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
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struct amdgpu_vm *vm,
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uint64_t start, uint64_t end,
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uint64_t dst, uint64_t flags)
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{
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@ -820,7 +821,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
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/* initialize the variables */
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addr = start;
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pt_idx = addr >> amdgpu_vm_block_size;
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pt = vm->page_tables[pt_idx].bo;
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pt = params->vm->page_tables[pt_idx].bo;
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if (params->shadow) {
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if (!pt->shadow)
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return;
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@ -843,7 +844,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
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/* walk over the address space and update the page tables */
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while (addr < end) {
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pt_idx = addr >> amdgpu_vm_block_size;
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pt = vm->page_tables[pt_idx].bo;
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pt = params->vm->page_tables[pt_idx].bo;
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if (params->shadow) {
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if (!pt->shadow)
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return;
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@ -894,7 +895,6 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
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* @flags: hw mapping flags
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*/
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static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
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struct amdgpu_vm *vm,
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uint64_t start, uint64_t end,
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uint64_t dst, uint64_t flags)
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{
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@ -928,25 +928,25 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
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if (params->src || !(flags & AMDGPU_PTE_VALID) ||
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(frag_start >= frag_end)) {
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amdgpu_vm_update_ptes(params, vm, start, end, dst, flags);
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amdgpu_vm_update_ptes(params, start, end, dst, flags);
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return;
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}
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/* handle the 4K area at the beginning */
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if (start != frag_start) {
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amdgpu_vm_update_ptes(params, vm, start, frag_start,
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amdgpu_vm_update_ptes(params, start, frag_start,
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dst, flags);
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dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
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}
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/* handle the area in the middle */
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amdgpu_vm_update_ptes(params, vm, frag_start, frag_end, dst,
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amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
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flags | frag_flags);
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/* handle the 4K area at the end */
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if (frag_end != end) {
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dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
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amdgpu_vm_update_ptes(params, vm, frag_end, end, dst, flags);
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amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
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}
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}
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@ -986,6 +986,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
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memset(¶ms, 0, sizeof(params));
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params.adev = adev;
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params.vm = vm;
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params.src = src;
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ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
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@ -1067,9 +1068,9 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
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goto error_free;
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params.shadow = true;
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amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags);
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amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
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params.shadow = false;
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amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags);
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amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
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amdgpu_ring_pad_ib(ring, params.ib);
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WARN_ON(params.ib->length_dw > ndw);
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