clocksource/drivers/timer-ti-dm: Simplify register writes with dmtimer_write()
We can simplify register write access by checking for the register write posted mode in the write function. This way we can combine the functions for __omap_dm_timer_write() and omap_dm_timer_write_reg() into a single function dmtimer_write(). We update the shared register access first, the timer revision specific register access will be updated in a later patch. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-4-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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@ -68,14 +68,29 @@ static inline u32 dmtimer_read(struct omap_dm_timer *timer, u32 reg)
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return readl_relaxed(timer->func_base + offset);
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}
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static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
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u32 reg, u32 val, int posted)
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/**
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* dmtimer_write - write timer registers in posted and non-posted mode
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* @timer: timer pointer over which write operation is to perform
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* @reg: lowest byte holds the register offset
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* @value: data to write into the register
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*
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* The posted mode bit is encoded in reg. Note that in posted mode, the write
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* pending bit must be checked. Otherwise a write on a register which has a
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* pending write will be lost.
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*/
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static inline void dmtimer_write(struct omap_dm_timer *timer, u32 reg, u32 val)
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{
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if (posted)
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while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
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u16 wp, offset;
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wp = reg >> WPSHIFT;
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offset = reg & 0xff;
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/* Wait for a possible write pending bit in posted mode */
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if (wp && timer->posted)
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while (readl_relaxed(timer->pend) & wp)
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cpu_relax();
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writel_relaxed(val, timer->func_base + (reg & 0xff));
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writel_relaxed(val, timer->func_base + offset);
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}
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static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
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@ -120,25 +135,24 @@ static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
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if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
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timer->posted = OMAP_TIMER_NONPOSTED;
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__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
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dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0);
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return;
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}
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__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
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OMAP_TIMER_CTRL_POSTED, 0);
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dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED);
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timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
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timer->posted = OMAP_TIMER_POSTED;
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}
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static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
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int posted, unsigned long rate)
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unsigned long rate)
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{
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u32 l;
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l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
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if (l & OMAP_TIMER_CTRL_ST) {
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l &= ~0x1;
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__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
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dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
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#ifdef CONFIG_ARCH_OMAP2PLUS
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/* Readback to make sure write has completed */
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dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
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@ -158,7 +172,7 @@ static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
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unsigned int value)
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{
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writel_relaxed(value, timer->irq_ena);
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__omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
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dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
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}
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static inline unsigned int
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@ -173,41 +187,17 @@ static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
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writel_relaxed(value, timer->irq_stat);
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}
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/**
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* omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
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* @timer: timer pointer over which write operation is to perform
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* @reg: lowest byte holds the register offset
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* @value: data to write into the register
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*
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* The posted mode bit is encoded in reg. Note that in posted mode the write
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* pending bit must be checked. Otherwise a write on a register which has a
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* pending write will be lost.
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*/
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static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
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u32 value)
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{
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WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
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__omap_dm_timer_write(timer, reg, value, timer->posted);
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}
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static void omap_timer_restore_context(struct omap_dm_timer *timer)
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{
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__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET,
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timer->context.ocp_cfg, 0);
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dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
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timer->context.twer);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
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timer->context.tcrr);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
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timer->context.tldr);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
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timer->context.tmar);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
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timer->context.tsicr);
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dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer);
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dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr);
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dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr);
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dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar);
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dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr);
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writel_relaxed(timer->context.tier, timer->irq_ena);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
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timer->context.tclr);
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dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr);
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}
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static void omap_timer_save_context(struct omap_dm_timer *timer)
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@ -256,7 +246,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *timer)
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if (timer->revision != 1)
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return -EINVAL;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
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dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
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do {
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l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET);
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@ -270,7 +260,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *timer)
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/* Configure timer for smart-idle mode */
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l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
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l |= 0x2 << 0x3;
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__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
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dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l);
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timer->posted = 0;
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@ -586,7 +576,7 @@ static int omap_dm_timer_start(struct omap_dm_timer *timer)
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l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
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if (!(l & OMAP_TIMER_CTRL_ST)) {
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l |= OMAP_TIMER_CTRL_ST;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
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}
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return 0;
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@ -602,7 +592,7 @@ static int omap_dm_timer_stop(struct omap_dm_timer *timer)
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if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
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rate = clk_get_rate(timer->fclk);
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__omap_dm_timer_stop(timer, timer->posted, rate);
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__omap_dm_timer_stop(timer, rate);
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omap_dm_timer_disable(timer);
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return 0;
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@ -615,7 +605,7 @@ static int omap_dm_timer_set_load(struct omap_dm_timer *timer,
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return -EINVAL;
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omap_dm_timer_enable(timer);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
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dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load);
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omap_dm_timer_disable(timer);
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return 0;
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@ -635,8 +625,8 @@ static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
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l |= OMAP_TIMER_CTRL_CE;
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else
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l &= ~OMAP_TIMER_CTRL_CE;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match);
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dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
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omap_dm_timer_disable(timer);
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return 0;
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@ -661,7 +651,7 @@ static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
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l |= trigger << 10;
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if (autoreload)
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l |= OMAP_TIMER_CTRL_AR;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
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omap_dm_timer_disable(timer);
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return 0;
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@ -696,7 +686,7 @@ static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
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l |= OMAP_TIMER_CTRL_PRE;
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l |= prescaler << 2;
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}
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
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omap_dm_timer_disable(timer);
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return 0;
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@ -736,7 +726,7 @@ static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
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writel_relaxed(l, timer->irq_dis);
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l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
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dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
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omap_dm_timer_disable(timer);
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return 0;
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@ -783,7 +773,7 @@ static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int
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return -EINVAL;
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}
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omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
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dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value);
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/* Save the context */
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timer->context.tcrr = value;
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