ARC updates for 4.12
- AXS10x platform clk updates for I2S, PGU - Adding region based cache flush operation for ARCv2 cores - Enforcing PAE40 dependency on HIGHMEM - ptrace support for additional regs in ARCv2 cores - Fix build failure in linux-next dut to a header include ordering change -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZEeokAAoJEGnX8d3iisJe/zgP/jpqauxaulNK4BvjJ3pI0+Fn Pgz5Mgd/S7MzmiDPsb3H0YSWQMlxcSop+EPk8V4jXcXyTuDDaC7NzWLuKau2rjiB jdbTycsJ4xSS5A8NrnG6AeE8SYAubJmtEwD8JASx+trtLGGHCKdTsRIOQpm5faUn W2IFaXs9Jof5ZYL5btOzmIOOTxdR6f3Aegq/Zqb6rxqD8ZmtVapjPdIlqQEB/xw4 JSbTH9+HxI1+vpzCuOb1Ba4sglfFG9kH0xxWvMN5HuoYsdXG5KfjoXVsxUIEl/RC m+bNdDOg5nlCS0U5PngnJnm5beBsAS8BApTTTM3ALNWGrsn+a6/1PraLsIgfa/yI XgcXp80/rGiFqAA3+fUw+ly1oJb06V9p4SRCOaOTErqcxofS4upbJ7oTu5z0HwMV HM2aw8vxZ2j4Wqrl5U3fGE9KvifUMJKuhcumpzfcmDsTtklCis4z13nbF0texNF2 tj0yqxYlOSdx4PoVzQG9Audf0sDeKUJ6Of+aGAXW55Zwq+QQJoCCzMSvTEV/xH4P RUIFkkhCQzshVmUDgHnWAjccrxz/LUrO1zLpwmOD0QWjfJHhyhegrlXGuKxNiRH5 rijMkOIe+Z8yG/UKqW0nvtB9svS0y9vqh3kEG1DJIRnNg7U2Fmk7rB404fGuvh4B T8uxDhsWP60hMZX1rw6h =zJ9B -----END PGP SIGNATURE----- Merge tag 'arc-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC updates from Vineet Gupta: - AXS10x platform clk updates for I2S, PGU - add region based cache flush operation for ARCv2 cores - enforce PAE40 dependency on HIGHMEM - ptrace support for additional regs in ARCv2 cores - fix build failure in linux-next dut to a header include ordering change * tag 'arc-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: Revert "ARCv2: Allow enabling PAE40 w/o HIGHMEM" ARC: mm: fix build failure in linux-next for UP builds ARCv2: ptrace: provide regset for accumulator/r30 regs elf: Add ARCv2 specific core note section ARCv2: mm: micro-optimize region flush generated code ARCv2: mm: Merge 2 updates to DC_CTRL for region flush ARCv2: mm: Implement cache region flush operations ARC: mm: Move full_page computation into cache version agnostic wrapper arc: axs10x: Fix ARC PGU default clock frequency arc: axs10x: Add DT bindings for I2S audio playback
This commit is contained in:
Linus Torvalds
Коммит
4a1e31c68e
|
|
@ -444,6 +444,7 @@ config ARC_HAS_PAE40
|
|||
bool "Support for the 40-bit Physical Address Extension"
|
||||
default n
|
||||
depends on ISA_ARCV2
|
||||
select HIGHMEM
|
||||
help
|
||||
Enable access to physical memory beyond 4G, only supported on
|
||||
ARC cores with 40 bit Physical Addressing support
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@
|
|||
pguclk: pguclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <74440000>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -149,12 +149,13 @@
|
|||
interrupts = <14>;
|
||||
};
|
||||
|
||||
i2c@0x1e000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
i2s: i2s@1e000 {
|
||||
compatible = "snps,designware-i2s";
|
||||
reg = <0x1e000 0x100>;
|
||||
clock-frequency = <400000>;
|
||||
clocks = <&i2cclk>;
|
||||
clocks = <&i2sclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
interrupts = <15>;
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
i2c@0x1f000 {
|
||||
|
|
@ -174,6 +175,7 @@
|
|||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,clock-delay = <0x03>;
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -295,5 +297,17 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
sound_playback {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "AXS10x HDMI Audio";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&adv7511>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -62,6 +62,8 @@ extern unsigned long perip_base, perip_end;
|
|||
#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
|
||||
#define ARC_REG_IC_IVIC 0x10
|
||||
#define ARC_REG_IC_CTRL 0x11
|
||||
#define ARC_REG_IC_IVIR 0x16
|
||||
#define ARC_REG_IC_ENDR 0x17
|
||||
#define ARC_REG_IC_IVIL 0x19
|
||||
#define ARC_REG_IC_PTAG 0x1E
|
||||
#define ARC_REG_IC_PTAG_HI 0x1F
|
||||
|
|
@ -76,6 +78,8 @@ extern unsigned long perip_base, perip_end;
|
|||
#define ARC_REG_DC_IVDL 0x4A
|
||||
#define ARC_REG_DC_FLSH 0x4B
|
||||
#define ARC_REG_DC_FLDL 0x4C
|
||||
#define ARC_REG_DC_STARTR 0x4D
|
||||
#define ARC_REG_DC_ENDR 0x4E
|
||||
#define ARC_REG_DC_PTAG 0x5C
|
||||
#define ARC_REG_DC_PTAG_HI 0x5F
|
||||
|
||||
|
|
@ -83,6 +87,8 @@ extern unsigned long perip_base, perip_end;
|
|||
#define DC_CTRL_DIS 0x001
|
||||
#define DC_CTRL_INV_MODE_FLUSH 0x040
|
||||
#define DC_CTRL_FLUSH_STATUS 0x100
|
||||
#define DC_CTRL_RGN_OP_INV 0x200
|
||||
#define DC_CTRL_RGN_OP_MSK 0x200
|
||||
|
||||
/*System-level cache (L2 cache) related Auxiliary registers */
|
||||
#define ARC_REG_SLC_CFG 0x901
|
||||
|
|
|
|||
|
|
@ -9,6 +9,10 @@
|
|||
#ifndef _ASM_ARC_MMU_H
|
||||
#define _ASM_ARC_MMU_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/threads.h> /* NR_CPUS */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARC_MMU_V1)
|
||||
#define CONFIG_ARC_MMU_VER 1
|
||||
#elif defined(CONFIG_ARC_MMU_V2)
|
||||
|
|
|
|||
|
|
@ -35,11 +35,11 @@
|
|||
#ifndef _ASM_ARC_PGTABLE_H
|
||||
#define _ASM_ARC_PGTABLE_H
|
||||
|
||||
#include <asm/page.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <linux/const.h>
|
||||
#define __ARCH_USE_5LEVEL_HACK
|
||||
#include <asm-generic/pgtable-nopmd.h>
|
||||
#include <linux/const.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/mmu.h> /* to propagate CONFIG_ARC_MMU_VER <n> */
|
||||
|
||||
/**************************************************************************
|
||||
* Page Table Flags
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ typedef unsigned long elf_greg_t;
|
|||
typedef unsigned long elf_fpregset_t;
|
||||
|
||||
#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
|
||||
#define ELF_ARCV2REG (sizeof(struct user_regs_arcv2) / sizeof(elf_greg_t))
|
||||
|
||||
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
|
||||
|
||||
|
|
|
|||
|
|
@ -47,6 +47,11 @@ struct user_regs_struct {
|
|||
unsigned long efa; /* break pt addr, for break points in delay slots */
|
||||
unsigned long stop_pc; /* give dbg stop_pc after ensuring brkpt trap */
|
||||
};
|
||||
|
||||
struct user_regs_arcv2 {
|
||||
unsigned long r30, r58, r59;
|
||||
};
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _UAPI__ASM_ARC_PTRACE_H */
|
||||
|
|
|
|||
|
|
@ -184,19 +184,75 @@ static int genregs_set(struct task_struct *target,
|
|||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
static int arcv2regs_get(struct task_struct *target,
|
||||
const struct user_regset *regset,
|
||||
unsigned int pos, unsigned int count,
|
||||
void *kbuf, void __user *ubuf)
|
||||
{
|
||||
const struct pt_regs *regs = task_pt_regs(target);
|
||||
int ret, copy_sz;
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS))
|
||||
copy_sz = sizeof(struct user_regs_arcv2);
|
||||
else
|
||||
copy_sz = 4; /* r30 only */
|
||||
|
||||
/*
|
||||
* itemized copy not needed like above as layout of regs (r30,r58,r59)
|
||||
* is exactly same in kernel (pt_regs) and userspace (user_regs_arcv2)
|
||||
*/
|
||||
ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, ®s->r30,
|
||||
0, copy_sz);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int arcv2regs_set(struct task_struct *target,
|
||||
const struct user_regset *regset,
|
||||
unsigned int pos, unsigned int count,
|
||||
const void *kbuf, const void __user *ubuf)
|
||||
{
|
||||
const struct pt_regs *regs = task_pt_regs(target);
|
||||
int ret, copy_sz;
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS))
|
||||
copy_sz = sizeof(struct user_regs_arcv2);
|
||||
else
|
||||
copy_sz = 4; /* r30 only */
|
||||
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, (void *)®s->r30,
|
||||
0, copy_sz);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
enum arc_getset {
|
||||
REGSET_GENERAL,
|
||||
REGSET_CMN,
|
||||
REGSET_ARCV2,
|
||||
};
|
||||
|
||||
static const struct user_regset arc_regsets[] = {
|
||||
[REGSET_GENERAL] = {
|
||||
[REGSET_CMN] = {
|
||||
.core_note_type = NT_PRSTATUS,
|
||||
.n = ELF_NGREG,
|
||||
.size = sizeof(unsigned long),
|
||||
.align = sizeof(unsigned long),
|
||||
.get = genregs_get,
|
||||
.set = genregs_set,
|
||||
}
|
||||
},
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
[REGSET_ARCV2] = {
|
||||
.core_note_type = NT_ARC_V2,
|
||||
.n = ELF_ARCV2REG,
|
||||
.size = sizeof(unsigned long),
|
||||
.align = sizeof(unsigned long),
|
||||
.get = arcv2regs_get,
|
||||
.set = arcv2regs_set,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static const struct user_regset_view user_arc_view = {
|
||||
|
|
|
|||
|
|
@ -21,6 +21,10 @@
|
|||
#include <asm/cachectl.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
#define USE_RGN_FLSH 1
|
||||
#endif
|
||||
|
||||
static int l2_line_sz;
|
||||
static int ioc_exists;
|
||||
int slc_enable = 1, ioc_enable = 1;
|
||||
|
|
@ -28,7 +32,7 @@ unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
|
|||
unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
|
||||
|
||||
void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr,
|
||||
unsigned long sz, const int cacheop);
|
||||
unsigned long sz, const int op, const int full_page);
|
||||
|
||||
void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz);
|
||||
void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz);
|
||||
|
|
@ -233,11 +237,10 @@ slc_chk:
|
|||
|
||||
static inline
|
||||
void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
|
||||
unsigned long sz, const int op)
|
||||
unsigned long sz, const int op, const int full_page)
|
||||
{
|
||||
unsigned int aux_cmd;
|
||||
int num_lines;
|
||||
const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
|
||||
|
||||
if (op == OP_INV_IC) {
|
||||
aux_cmd = ARC_REG_IC_IVIL;
|
||||
|
|
@ -279,11 +282,10 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
|
|||
*/
|
||||
static inline
|
||||
void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
|
||||
unsigned long sz, const int op)
|
||||
unsigned long sz, const int op, const int full_page)
|
||||
{
|
||||
unsigned int aux_cmd, aux_tag;
|
||||
int num_lines;
|
||||
const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
|
||||
|
||||
if (op == OP_INV_IC) {
|
||||
aux_cmd = ARC_REG_IC_IVIL;
|
||||
|
|
@ -334,6 +336,8 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
|
|||
}
|
||||
}
|
||||
|
||||
#ifndef USE_RGN_FLSH
|
||||
|
||||
/*
|
||||
* In HS38x (MMU v4), I-cache is VIPT (can alias), D-cache is PIPT
|
||||
* Here's how cache ops are implemented
|
||||
|
|
@ -349,17 +353,16 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
|
|||
*/
|
||||
static inline
|
||||
void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
|
||||
unsigned long sz, const int cacheop)
|
||||
unsigned long sz, const int op, const int full_page)
|
||||
{
|
||||
unsigned int aux_cmd;
|
||||
int num_lines;
|
||||
const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE;
|
||||
|
||||
if (cacheop == OP_INV_IC) {
|
||||
if (op == OP_INV_IC) {
|
||||
aux_cmd = ARC_REG_IC_IVIL;
|
||||
} else {
|
||||
/* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
|
||||
aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
|
||||
aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
|
||||
}
|
||||
|
||||
/* Ensure we properly floor/ceil the non-line aligned/sized requests
|
||||
|
|
@ -368,7 +371,7 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
|
|||
* -@paddr will be cache-line aligned already (being page aligned)
|
||||
* -@sz will be integral multiple of line size (being page sized).
|
||||
*/
|
||||
if (!full_page_op) {
|
||||
if (!full_page) {
|
||||
sz += paddr & ~CACHE_LINE_MASK;
|
||||
paddr &= CACHE_LINE_MASK;
|
||||
}
|
||||
|
|
@ -381,7 +384,7 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
|
|||
* - (and needs to be written before the lower 32 bits)
|
||||
*/
|
||||
if (is_pae40_enabled()) {
|
||||
if (cacheop == OP_INV_IC)
|
||||
if (op == OP_INV_IC)
|
||||
/*
|
||||
* Non aliasing I-cache in HS38,
|
||||
* aliasing I-cache handled in __cache_line_loop_v3()
|
||||
|
|
@ -397,6 +400,55 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
|
|||
}
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* optimized flush operation which takes a region as opposed to iterating per line
|
||||
*/
|
||||
static inline
|
||||
void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
|
||||
unsigned long sz, const int op, const int full_page)
|
||||
{
|
||||
unsigned int s, e;
|
||||
|
||||
/* Only for Non aliasing I-cache in HS38 */
|
||||
if (op == OP_INV_IC) {
|
||||
s = ARC_REG_IC_IVIR;
|
||||
e = ARC_REG_IC_ENDR;
|
||||
} else {
|
||||
s = ARC_REG_DC_STARTR;
|
||||
e = ARC_REG_DC_ENDR;
|
||||
}
|
||||
|
||||
if (!full_page) {
|
||||
/* for any leading gap between @paddr and start of cache line */
|
||||
sz += paddr & ~CACHE_LINE_MASK;
|
||||
paddr &= CACHE_LINE_MASK;
|
||||
|
||||
/*
|
||||
* account for any trailing gap to end of cache line
|
||||
* this is equivalent to DIV_ROUND_UP() in line ops above
|
||||
*/
|
||||
sz += L1_CACHE_BYTES - 1;
|
||||
}
|
||||
|
||||
if (is_pae40_enabled()) {
|
||||
/* TBD: check if crossing 4TB boundary */
|
||||
if (op == OP_INV_IC)
|
||||
write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
|
||||
else
|
||||
write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
|
||||
}
|
||||
|
||||
/* ENDR needs to be set ahead of START */
|
||||
write_aux_reg(e, paddr + sz); /* ENDR is exclusive */
|
||||
write_aux_reg(s, paddr);
|
||||
|
||||
/* caller waits on DC_CTRL.FS */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (CONFIG_ARC_MMU_VER < 3)
|
||||
#define __cache_line_loop __cache_line_loop_v2
|
||||
#elif (CONFIG_ARC_MMU_VER == 3)
|
||||
|
|
@ -411,6 +463,11 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
|
|||
* Machine specific helpers for Entire D-Cache or Per Line ops
|
||||
*/
|
||||
|
||||
#ifndef USE_RGN_FLSH
|
||||
/*
|
||||
* this version avoids extra read/write of DC_CTRL for flush or invalid ops
|
||||
* in the non region flush regime (such as for ARCompact)
|
||||
*/
|
||||
static inline void __before_dc_op(const int op)
|
||||
{
|
||||
if (op == OP_FLUSH_N_INV) {
|
||||
|
|
@ -424,6 +481,32 @@ static inline void __before_dc_op(const int op)
|
|||
}
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline void __before_dc_op(const int op)
|
||||
{
|
||||
const unsigned int ctl = ARC_REG_DC_CTRL;
|
||||
unsigned int val = read_aux_reg(ctl);
|
||||
|
||||
if (op == OP_FLUSH_N_INV) {
|
||||
val |= DC_CTRL_INV_MODE_FLUSH;
|
||||
}
|
||||
|
||||
if (op != OP_INV_IC) {
|
||||
/*
|
||||
* Flush / Invalidate is provided by DC_CTRL.RNG_OP 0 or 1
|
||||
* combined Flush-n-invalidate uses DC_CTRL.IM = 1 set above
|
||||
*/
|
||||
val &= ~DC_CTRL_RGN_OP_MSK;
|
||||
if (op & OP_INV)
|
||||
val |= DC_CTRL_RGN_OP_INV;
|
||||
}
|
||||
write_aux_reg(ctl, val);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static inline void __after_dc_op(const int op)
|
||||
{
|
||||
if (op & OP_FLUSH) {
|
||||
|
|
@ -486,13 +569,14 @@ static void __dc_enable(void)
|
|||
static inline void __dc_line_op(phys_addr_t paddr, unsigned long vaddr,
|
||||
unsigned long sz, const int op)
|
||||
{
|
||||
const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
__before_dc_op(op);
|
||||
|
||||
__cache_line_loop(paddr, vaddr, sz, op);
|
||||
__cache_line_loop(paddr, vaddr, sz, op, full_page);
|
||||
|
||||
__after_dc_op(op);
|
||||
|
||||
|
|
@ -521,10 +605,11 @@ static inline void
|
|||
__ic_line_inv_vaddr_local(phys_addr_t paddr, unsigned long vaddr,
|
||||
unsigned long sz)
|
||||
{
|
||||
const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
(*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC);
|
||||
(*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC, full_page);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -419,7 +419,7 @@ typedef struct elf64_shdr {
|
|||
#define NT_METAG_CBUF 0x500 /* Metag catch buffer registers */
|
||||
#define NT_METAG_RPIPE 0x501 /* Metag read pipeline state */
|
||||
#define NT_METAG_TLS 0x502 /* Metag TLS pointer */
|
||||
|
||||
#define NT_ARC_V2 0x600 /* ARCv2 accumulator/extra registers */
|
||||
|
||||
/* Note header in a PT_NOTE section */
|
||||
typedef struct elf32_note {
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче