drm/i915/guc: New GuC interrupt register for Gen11
Gen11 defines new more flexible Host-to-GuC interrupt register. Now the host can write any 32-bit payload to trigger an interrupt and GuC can additionally read this payload from the register. Current GuC firmware ignores the payload so we just write 0. Bspec: 21043 Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190527183613.17076-9-michal.wajdeczko@intel.com
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@ -34,6 +34,13 @@ static void gen8_guc_raise_irq(struct intel_guc *guc)
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I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
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}
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static void gen11_guc_raise_irq(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
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}
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static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
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{
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GEM_BUG_ON(!guc->send_regs.base);
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@ -63,6 +70,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
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void intel_guc_init_early(struct intel_guc *guc)
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{
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struct drm_i915_private *i915 = guc_to_i915(guc);
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intel_guc_fw_init_early(guc);
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intel_guc_ct_init_early(&guc->ct);
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intel_guc_log_init_early(&guc->log);
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@ -71,7 +80,10 @@ void intel_guc_init_early(struct intel_guc *guc)
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spin_lock_init(&guc->irq_lock);
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guc->send = intel_guc_send_nop;
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guc->handler = intel_guc_to_host_event_handler_nop;
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guc->notify = gen8_guc_raise_irq;
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if (INTEL_GEN(i915) >= 11)
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guc->notify = gen11_guc_raise_irq;
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else
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guc->notify = gen8_guc_raise_irq;
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}
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static int guc_init_wq(struct intel_guc *guc)
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@ -103,6 +103,7 @@
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#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
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#define GUC_SEND_TRIGGER (1<<0)
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#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
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#define GUC_NUM_DOORBELLS 256
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