bnx2x: HW lock mechanism
HW lock mechanism Enhancing the HW lock to work per function and not only per port - this is needed for the next patch that protects races over HW attention detection between the different functions. At this chance, changing the functions names to be more inline with the current naming convention Signed-off-by: Yitchak Gertner <gertner@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yitchak Gertner
David S. Miller
Родитель
da5a662a23
Коммит
4a37fb660c
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@ -1693,11 +1693,12 @@ static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
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* General service functions
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*/
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static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
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static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
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{
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u32 lock_status;
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u32 resource_bit = (1 << resource);
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u8 port = BP_PORT(bp);
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int func = BP_FUNC(bp);
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u32 hw_lock_control_reg;
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int cnt;
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/* Validating that the resource is within range */
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@ -1708,8 +1709,15 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
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return -EINVAL;
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}
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if (func <= 5) {
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hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
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} else {
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hw_lock_control_reg =
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(MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
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}
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/* Validating that the resource is not already taken */
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lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
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lock_status = REG_RD(bp, hw_lock_control_reg);
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if (lock_status & resource_bit) {
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DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
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lock_status, resource_bit);
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@ -1719,9 +1727,8 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
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/* Try for 1 second every 5ms */
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for (cnt = 0; cnt < 200; cnt++) {
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/* Try to acquire the lock */
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REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8 + 4,
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resource_bit);
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lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
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REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
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lock_status = REG_RD(bp, hw_lock_control_reg);
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if (lock_status & resource_bit)
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return 0;
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@ -1731,11 +1738,12 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
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return -EAGAIN;
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}
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static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
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static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
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{
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u32 lock_status;
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u32 resource_bit = (1 << resource);
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u8 port = BP_PORT(bp);
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int func = BP_FUNC(bp);
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u32 hw_lock_control_reg;
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/* Validating that the resource is within range */
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if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
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@ -1745,20 +1753,27 @@ static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
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return -EINVAL;
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}
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if (func <= 5) {
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hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
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} else {
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hw_lock_control_reg =
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(MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
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}
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/* Validating that the resource is currently taken */
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lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
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lock_status = REG_RD(bp, hw_lock_control_reg);
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if (!(lock_status & resource_bit)) {
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DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
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lock_status, resource_bit);
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return -EFAULT;
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}
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REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8, resource_bit);
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REG_WR(bp, hw_lock_control_reg, resource_bit);
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return 0;
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}
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/* HW Lock for shared dual port PHYs */
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static void bnx2x_phy_hw_lock(struct bnx2x *bp)
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static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
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{
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u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
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@ -1766,16 +1781,16 @@ static void bnx2x_phy_hw_lock(struct bnx2x *bp)
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if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
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(ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
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bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
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bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
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}
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static void bnx2x_phy_hw_unlock(struct bnx2x *bp)
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static void bnx2x_release_phy_lock(struct bnx2x *bp)
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{
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u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
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if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
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(ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
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bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
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bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
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mutex_unlock(&bp->port.phy_mutex);
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}
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@ -1795,7 +1810,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
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return -EINVAL;
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}
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bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
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bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
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/* read GPIO and mask except the float bits */
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gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
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@ -1828,7 +1843,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
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}
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REG_WR(bp, MISC_REG_GPIO, gpio_reg);
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bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_GPIO);
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bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
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return 0;
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}
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@ -1844,7 +1859,7 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
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return -EINVAL;
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}
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bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
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bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
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/* read SPIO and mask except the float bits */
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spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
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@ -1874,7 +1889,7 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
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}
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REG_WR(bp, MISC_REG_SPIO, spio_reg);
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bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_SPIO);
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bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
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return 0;
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}
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@ -1940,9 +1955,9 @@ static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
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/* Initialize link parameters structure variables */
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bp->link_params.mtu = bp->dev->mtu;
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bnx2x_phy_hw_lock(bp);
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bnx2x_acquire_phy_lock(bp);
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rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
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bnx2x_phy_hw_unlock(bp);
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bnx2x_release_phy_lock(bp);
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if (bp->link_vars.link_up)
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bnx2x_link_report(bp);
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@ -1958,9 +1973,9 @@ static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
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static void bnx2x_link_set(struct bnx2x *bp)
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{
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if (!BP_NOMCP(bp)) {
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bnx2x_phy_hw_lock(bp);
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bnx2x_acquire_phy_lock(bp);
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bnx2x_phy_init(&bp->link_params, &bp->link_vars);
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bnx2x_phy_hw_unlock(bp);
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bnx2x_release_phy_lock(bp);
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bnx2x_calc_fc_adv(bp);
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} else
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@ -1970,9 +1985,9 @@ static void bnx2x_link_set(struct bnx2x *bp)
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static void bnx2x__link_reset(struct bnx2x *bp)
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{
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if (!BP_NOMCP(bp)) {
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bnx2x_phy_hw_lock(bp);
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bnx2x_acquire_phy_lock(bp);
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bnx2x_link_reset(&bp->link_params, &bp->link_vars);
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bnx2x_phy_hw_unlock(bp);
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bnx2x_release_phy_lock(bp);
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} else
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BNX2X_ERR("Bootcode is missing -not resetting link\n");
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}
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@ -1981,9 +1996,9 @@ static u8 bnx2x_link_test(struct bnx2x *bp)
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{
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u8 rc;
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bnx2x_phy_hw_lock(bp);
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bnx2x_acquire_phy_lock(bp);
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rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
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bnx2x_phy_hw_unlock(bp);
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bnx2x_release_phy_lock(bp);
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return rc;
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}
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@ -2207,9 +2222,9 @@ static void bnx2x_link_attn(struct bnx2x *bp)
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/* Make sure that we are synced with the current statistics */
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bnx2x_stats_handle(bp, STATS_EVENT_STOP);
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bnx2x_phy_hw_lock(bp);
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bnx2x_acquire_phy_lock(bp);
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bnx2x_link_update(&bp->link_params, &bp->link_vars);
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bnx2x_phy_hw_unlock(bp);
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bnx2x_release_phy_lock(bp);
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if (bp->link_vars.link_up) {
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@ -2361,7 +2376,7 @@ static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
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}
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/* acquire split MCP access lock register */
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static int bnx2x_lock_alr(struct bnx2x *bp)
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static int bnx2x_acquire_alr(struct bnx2x *bp)
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{
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u32 i, j, val;
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int rc = 0;
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@ -2385,8 +2400,8 @@ static int bnx2x_lock_alr(struct bnx2x *bp)
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return rc;
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}
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/* Release split MCP access lock register */
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static void bnx2x_unlock_alr(struct bnx2x *bp)
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/* release split MCP access lock register */
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static void bnx2x_release_alr(struct bnx2x *bp)
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{
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u32 val = 0;
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@ -2399,7 +2414,6 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
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u16 rc = 0;
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barrier(); /* status block is written to by the chip */
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if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
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bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
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rc |= 1;
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@ -2706,7 +2720,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
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/* need to take HW lock because MCP or other port might also
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try to handle this event */
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bnx2x_lock_alr(bp);
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bnx2x_acquire_alr(bp);
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attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
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attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
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@ -2742,7 +2756,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
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}
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}
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bnx2x_unlock_alr(bp);
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bnx2x_release_alr(bp);
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reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8;
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@ -6767,7 +6781,7 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
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/* Check if it is the UNDI driver
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* UNDI driver initializes CID offset for normal bell to 0x7
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*/
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bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
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bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
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val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
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if (val == 0x7) {
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u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
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@ -6846,7 +6860,7 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
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(SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
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DRV_MSG_SEQ_NUMBER_MASK);
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}
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bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_UNDI);
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bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
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}
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}
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@ -7703,11 +7717,11 @@ static void bnx2x_get_drvinfo(struct net_device *dev,
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phy_fw_ver[0] = '\0';
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if (bp->port.pmf) {
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bnx2x_phy_hw_lock(bp);
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bnx2x_acquire_phy_lock(bp);
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bnx2x_get_ext_phy_fw_version(&bp->link_params,
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(bp->state != BNX2X_STATE_CLOSED),
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phy_fw_ver, PHY_FW_VER_LEN);
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bnx2x_phy_hw_unlock(bp);
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bnx2x_release_phy_lock(bp);
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}
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snprintf(info->fw_version, 32, "%d.%d.%d:%d BC:%x%s%s",
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@ -8165,7 +8179,7 @@ static int bnx2x_set_eeprom(struct net_device *dev,
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if (eeprom->magic == 0x00504859)
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if (bp->port.pmf) {
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bnx2x_phy_hw_lock(bp);
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bnx2x_acquire_phy_lock(bp);
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rc = bnx2x_flash_download(bp, BP_PORT(bp),
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bp->link_params.ext_phy_config,
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(bp->state != BNX2X_STATE_CLOSED),
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@ -8177,7 +8191,7 @@ static int bnx2x_set_eeprom(struct net_device *dev,
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rc |= bnx2x_phy_init(&bp->link_params,
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&bp->link_vars);
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}
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bnx2x_phy_hw_unlock(bp);
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bnx2x_release_phy_lock(bp);
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} else /* Only the PMF can access the PHY */
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return -EINVAL;
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@ -8601,15 +8615,15 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
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if (loopback_mode == BNX2X_MAC_LOOPBACK) {
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bp->link_params.loopback_mode = LOOPBACK_BMAC;
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bnx2x_phy_hw_lock(bp);
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bnx2x_acquire_phy_lock(bp);
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bnx2x_phy_init(&bp->link_params, &bp->link_vars);
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bnx2x_phy_hw_unlock(bp);
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bnx2x_release_phy_lock(bp);
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} else if (loopback_mode == BNX2X_PHY_LOOPBACK) {
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bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
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bnx2x_phy_hw_lock(bp);
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bnx2x_acquire_phy_lock(bp);
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bnx2x_phy_init(&bp->link_params, &bp->link_vars);
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bnx2x_phy_hw_unlock(bp);
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bnx2x_release_phy_lock(bp);
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/* wait until link state is restored */
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bnx2x_wait_for_link(bp, link_up);
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@ -1372,6 +1372,23 @@
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be asserted). */
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#define MISC_REG_DRIVER_CONTROL_16 0xa5f0
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#define MISC_REG_DRIVER_CONTROL_16_SIZE 2
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/* [RW 32] The following driver registers(1...16) represent 16 drivers and
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32 clients. Each client can be controlled by one driver only. One in each
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bit represent that this driver control the appropriate client (Ex: bit 5
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is set means this driver control client number 5). addr1 = set; addr0 =
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clear; read from both addresses will give the same result = status. write
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to address 1 will set a request to control all the clients that their
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appropriate bit (in the write command) is set. if the client is free (the
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appropriate bit in all the other drivers is clear) one will be written to
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that driver register; if the client isn't free the bit will remain zero.
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if the appropriate bit is set (the driver request to gain control on a
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client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
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interrupt will be asserted). write to address 0 will set a request to
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free all the clients that their appropriate bit (in the write command) is
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set. if the appropriate bit is clear (the driver request to free a client
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it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
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be asserted). */
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#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
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/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
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only. */
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#define MISC_REG_E1HMF_MODE 0xa5f8
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