staging: sm7xxfb: minor maintenance on timing path
This patch keeps smtc_set_timing and sm7xx_set_timing functions closed to smtcfb_setmode. This change eases reviewing and maintaining this logic path. Tested with SM712. Signed-off-by: Javier M. Mellid <jmunhoz@igalia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Javier M. Mellid
Greg Kroah-Hartman
Родитель
0f9af641f2
Коммит
4a7c2e0d73
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@ -135,125 +135,6 @@ static int __init sm7xx_vga_setup(char *options)
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}
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__setup("vga=", sm7xx_vga_setup);
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static void sm7xx_set_timing(struct smtcfb_info *sfb)
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{
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int i = 0, j = 0;
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u32 m_nScreenStride;
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dev_dbg(&sfb->pdev->dev,
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"sfb->width=%d sfb->height=%d "
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"sfb->fb.var.bits_per_pixel=%d sfb->hz=%d\n",
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sfb->width, sfb->height, sfb->fb.var.bits_per_pixel, sfb->hz);
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for (j = 0; j < numVGAModes; j++) {
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if (VGAMode[j].mmSizeX == sfb->width &&
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VGAMode[j].mmSizeY == sfb->height &&
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VGAMode[j].bpp == sfb->fb.var.bits_per_pixel &&
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VGAMode[j].hz == sfb->hz) {
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dev_dbg(&sfb->pdev->dev,
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"VGAMode[j].mmSizeX=%d VGAMode[j].mmSizeY=%d "
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"VGAMode[j].bpp=%d VGAMode[j].hz=%d\n",
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VGAMode[j].mmSizeX, VGAMode[j].mmSizeY,
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VGAMode[j].bpp, VGAMode[j].hz);
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dev_dbg(&sfb->pdev->dev, "VGAMode index=%d\n", j);
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smtc_mmiowb(0x0, 0x3c6);
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smtc_seqw(0, 0x1);
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smtc_mmiowb(VGAMode[j].Init_MISC, 0x3c2);
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/* init SEQ register SR00 - SR04 */
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for (i = 0; i < SIZE_SR00_SR04; i++)
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smtc_seqw(i, VGAMode[j].Init_SR00_SR04[i]);
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/* init SEQ register SR10 - SR24 */
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for (i = 0; i < SIZE_SR10_SR24; i++)
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smtc_seqw(i + 0x10,
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VGAMode[j].Init_SR10_SR24[i]);
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/* init SEQ register SR30 - SR75 */
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for (i = 0; i < SIZE_SR30_SR75; i++)
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if (((i + 0x30) != 0x62) \
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&& ((i + 0x30) != 0x6a) \
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&& ((i + 0x30) != 0x6b))
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smtc_seqw(i + 0x30,
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VGAMode[j].Init_SR30_SR75[i]);
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/* init SEQ register SR80 - SR93 */
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for (i = 0; i < SIZE_SR80_SR93; i++)
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smtc_seqw(i + 0x80,
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VGAMode[j].Init_SR80_SR93[i]);
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/* init SEQ register SRA0 - SRAF */
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for (i = 0; i < SIZE_SRA0_SRAF; i++)
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smtc_seqw(i + 0xa0,
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VGAMode[j].Init_SRA0_SRAF[i]);
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/* init Graphic register GR00 - GR08 */
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for (i = 0; i < SIZE_GR00_GR08; i++)
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smtc_grphw(i, VGAMode[j].Init_GR00_GR08[i]);
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/* init Attribute register AR00 - AR14 */
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for (i = 0; i < SIZE_AR00_AR14; i++)
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smtc_attrw(i, VGAMode[j].Init_AR00_AR14[i]);
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/* init CRTC register CR00 - CR18 */
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for (i = 0; i < SIZE_CR00_CR18; i++)
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smtc_crtcw(i, VGAMode[j].Init_CR00_CR18[i]);
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/* init CRTC register CR30 - CR4D */
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for (i = 0; i < SIZE_CR30_CR4D; i++)
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smtc_crtcw(i + 0x30,
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VGAMode[j].Init_CR30_CR4D[i]);
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/* init CRTC register CR90 - CRA7 */
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for (i = 0; i < SIZE_CR90_CRA7; i++)
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smtc_crtcw(i + 0x90,
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VGAMode[j].Init_CR90_CRA7[i]);
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}
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}
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smtc_mmiowb(0x67, 0x3c2);
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/* set VPR registers */
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writel(0x0, sfb->m_pVPR + 0x0C);
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writel(0x0, sfb->m_pVPR + 0x40);
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/* set data width */
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m_nScreenStride =
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(sfb->width * sfb->fb.var.bits_per_pixel) / 64;
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switch (sfb->fb.var.bits_per_pixel) {
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case 8:
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writel(0x0, sfb->m_pVPR + 0x0);
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break;
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case 16:
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writel(0x00020000, sfb->m_pVPR + 0x0);
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break;
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case 24:
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writel(0x00040000, sfb->m_pVPR + 0x0);
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break;
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case 32:
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writel(0x00030000, sfb->m_pVPR + 0x0);
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break;
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}
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writel((u32) (((m_nScreenStride + 2) << 16) | m_nScreenStride),
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sfb->m_pVPR + 0x10);
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}
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static void smtc_set_timing(struct smtcfb_info *sfb)
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{
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switch (sfb->chip_id) {
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case 0x710:
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case 0x712:
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case 0x720:
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sm7xx_set_timing(sfb);
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break;
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}
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}
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static void sm712_setpalette(int regno, unsigned red, unsigned green,
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unsigned blue, struct fb_info *info)
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{
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@ -581,6 +462,125 @@ smtcfb_write(struct fb_info *info, const char __user *buf, size_t count,
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}
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#endif /* ! __BIG_ENDIAN */
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static void sm7xx_set_timing(struct smtcfb_info *sfb)
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{
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int i = 0, j = 0;
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u32 m_nScreenStride;
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dev_dbg(&sfb->pdev->dev,
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"sfb->width=%d sfb->height=%d "
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"sfb->fb.var.bits_per_pixel=%d sfb->hz=%d\n",
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sfb->width, sfb->height, sfb->fb.var.bits_per_pixel, sfb->hz);
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for (j = 0; j < numVGAModes; j++) {
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if (VGAMode[j].mmSizeX == sfb->width &&
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VGAMode[j].mmSizeY == sfb->height &&
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VGAMode[j].bpp == sfb->fb.var.bits_per_pixel &&
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VGAMode[j].hz == sfb->hz) {
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dev_dbg(&sfb->pdev->dev,
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"VGAMode[j].mmSizeX=%d VGAMode[j].mmSizeY=%d "
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"VGAMode[j].bpp=%d VGAMode[j].hz=%d\n",
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VGAMode[j].mmSizeX, VGAMode[j].mmSizeY,
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VGAMode[j].bpp, VGAMode[j].hz);
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dev_dbg(&sfb->pdev->dev, "VGAMode index=%d\n", j);
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smtc_mmiowb(0x0, 0x3c6);
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smtc_seqw(0, 0x1);
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smtc_mmiowb(VGAMode[j].Init_MISC, 0x3c2);
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/* init SEQ register SR00 - SR04 */
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for (i = 0; i < SIZE_SR00_SR04; i++)
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smtc_seqw(i, VGAMode[j].Init_SR00_SR04[i]);
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/* init SEQ register SR10 - SR24 */
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for (i = 0; i < SIZE_SR10_SR24; i++)
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smtc_seqw(i + 0x10,
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VGAMode[j].Init_SR10_SR24[i]);
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/* init SEQ register SR30 - SR75 */
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for (i = 0; i < SIZE_SR30_SR75; i++)
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if (((i + 0x30) != 0x62) \
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&& ((i + 0x30) != 0x6a) \
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&& ((i + 0x30) != 0x6b))
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smtc_seqw(i + 0x30,
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VGAMode[j].Init_SR30_SR75[i]);
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/* init SEQ register SR80 - SR93 */
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for (i = 0; i < SIZE_SR80_SR93; i++)
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smtc_seqw(i + 0x80,
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VGAMode[j].Init_SR80_SR93[i]);
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/* init SEQ register SRA0 - SRAF */
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for (i = 0; i < SIZE_SRA0_SRAF; i++)
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smtc_seqw(i + 0xa0,
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VGAMode[j].Init_SRA0_SRAF[i]);
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/* init Graphic register GR00 - GR08 */
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for (i = 0; i < SIZE_GR00_GR08; i++)
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smtc_grphw(i, VGAMode[j].Init_GR00_GR08[i]);
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/* init Attribute register AR00 - AR14 */
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for (i = 0; i < SIZE_AR00_AR14; i++)
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smtc_attrw(i, VGAMode[j].Init_AR00_AR14[i]);
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/* init CRTC register CR00 - CR18 */
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for (i = 0; i < SIZE_CR00_CR18; i++)
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smtc_crtcw(i, VGAMode[j].Init_CR00_CR18[i]);
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/* init CRTC register CR30 - CR4D */
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for (i = 0; i < SIZE_CR30_CR4D; i++)
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smtc_crtcw(i + 0x30,
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VGAMode[j].Init_CR30_CR4D[i]);
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/* init CRTC register CR90 - CRA7 */
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for (i = 0; i < SIZE_CR90_CRA7; i++)
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smtc_crtcw(i + 0x90,
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VGAMode[j].Init_CR90_CRA7[i]);
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}
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}
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smtc_mmiowb(0x67, 0x3c2);
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/* set VPR registers */
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writel(0x0, sfb->m_pVPR + 0x0C);
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writel(0x0, sfb->m_pVPR + 0x40);
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/* set data width */
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m_nScreenStride =
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(sfb->width * sfb->fb.var.bits_per_pixel) / 64;
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switch (sfb->fb.var.bits_per_pixel) {
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case 8:
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writel(0x0, sfb->m_pVPR + 0x0);
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break;
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case 16:
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writel(0x00020000, sfb->m_pVPR + 0x0);
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break;
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case 24:
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writel(0x00040000, sfb->m_pVPR + 0x0);
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break;
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case 32:
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writel(0x00030000, sfb->m_pVPR + 0x0);
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break;
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}
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writel((u32) (((m_nScreenStride + 2) << 16) | m_nScreenStride),
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sfb->m_pVPR + 0x10);
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}
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static void smtc_set_timing(struct smtcfb_info *sfb)
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{
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switch (sfb->chip_id) {
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case 0x710:
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case 0x712:
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case 0x720:
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sm7xx_set_timing(sfb);
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break;
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}
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}
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void smtcfb_setmode(struct smtcfb_info *sfb)
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{
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switch (sfb->fb.var.bits_per_pixel) {
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