qed: Semantic refactoring of interrupt code
Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Родитель
64d4e3431e
Коммит
4ac801b77e
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@ -1011,13 +1011,17 @@ static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
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{
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u32 *resc_start = p_hwfn->hw_info.resc_start;
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u32 *resc_num = p_hwfn->hw_info.resc_num;
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struct qed_sb_cnt_info sb_cnt_info;
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int num_funcs, i;
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num_funcs = MAX_NUM_PFS_BB;
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memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
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qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
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resc_num[QED_SB] = min_t(u32,
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(MAX_SB_PER_PATH_BB / num_funcs),
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qed_int_get_num_sbs(p_hwfn, NULL));
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sb_cnt_info.sb_cnt);
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resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
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resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
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resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
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@ -343,17 +343,17 @@ void qed_int_sp_dpc(unsigned long hwfn_cookie)
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static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn)
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{
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struct qed_dev *cdev = p_hwfn->cdev;
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struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
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struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
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if (p_sb) {
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if (p_sb->sb_attn)
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dma_free_coherent(&cdev->pdev->dev,
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SB_ATTN_ALIGNED_SIZE(p_hwfn),
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p_sb->sb_attn,
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p_sb->sb_phys);
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kfree(p_sb);
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}
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if (!p_sb)
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return;
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if (p_sb->sb_attn)
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dma_free_coherent(&p_hwfn->cdev->pdev->dev,
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SB_ATTN_ALIGNED_SIZE(p_hwfn),
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p_sb->sb_attn,
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p_sb->sb_phys);
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kfree(p_sb);
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}
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static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn,
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@ -433,6 +433,7 @@ void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
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u16 vf_number,
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u8 vf_valid)
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{
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struct qed_dev *cdev = p_hwfn->cdev;
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u32 cau_state;
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memset(p_sb_entry, 0, sizeof(*p_sb_entry));
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@ -451,14 +452,12 @@ void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
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cau_state = CAU_HC_DISABLE_STATE;
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if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
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if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
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cau_state = CAU_HC_ENABLE_STATE;
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if (!p_hwfn->cdev->rx_coalesce_usecs)
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p_hwfn->cdev->rx_coalesce_usecs =
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QED_CAU_DEF_RX_USECS;
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if (!p_hwfn->cdev->tx_coalesce_usecs)
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p_hwfn->cdev->tx_coalesce_usecs =
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QED_CAU_DEF_TX_USECS;
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if (!cdev->rx_coalesce_usecs)
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cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS;
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if (!cdev->tx_coalesce_usecs)
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cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS;
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}
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SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
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@ -638,8 +637,10 @@ int qed_int_sb_release(struct qed_hwfn *p_hwfn,
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sb_info->sb_ack = 0;
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memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
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p_hwfn->sbs_info[sb_id] = NULL;
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p_hwfn->num_sbs--;
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if (p_hwfn->sbs_info[sb_id] != NULL) {
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p_hwfn->sbs_info[sb_id] = NULL;
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p_hwfn->num_sbs--;
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}
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return 0;
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}
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@ -648,14 +649,15 @@ static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)
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{
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struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
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if (p_sb) {
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if (p_sb->sb_info.sb_virt)
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dma_free_coherent(&p_hwfn->cdev->pdev->dev,
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SB_ALIGNED_SIZE(p_hwfn),
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p_sb->sb_info.sb_virt,
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p_sb->sb_info.sb_phys);
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kfree(p_sb);
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}
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if (!p_sb)
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return;
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if (p_sb->sb_info.sb_virt)
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dma_free_coherent(&p_hwfn->cdev->pdev->dev,
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SB_ALIGNED_SIZE(p_hwfn),
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p_sb->sb_info.sb_virt,
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p_sb->sb_info.sb_phys);
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kfree(p_sb);
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}
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static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn,
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@ -718,36 +720,36 @@ int qed_int_register_cb(struct qed_hwfn *p_hwfn,
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__le16 **p_fw_cons)
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{
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struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
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int qed_status = -ENOMEM;
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int rc = -ENOMEM;
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u8 pi;
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/* Look for a free index */
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for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
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if (!p_sp_sb->pi_info_arr[pi].comp_cb) {
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p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
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p_sp_sb->pi_info_arr[pi].cookie = cookie;
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*sb_idx = pi;
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*p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
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qed_status = 0;
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break;
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}
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if (p_sp_sb->pi_info_arr[pi].comp_cb)
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continue;
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p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
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p_sp_sb->pi_info_arr[pi].cookie = cookie;
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*sb_idx = pi;
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*p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
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rc = 0;
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break;
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}
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return qed_status;
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return rc;
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}
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int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)
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{
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struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
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int qed_status = -ENOMEM;
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if (p_sp_sb->pi_info_arr[pi].comp_cb) {
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p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
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p_sp_sb->pi_info_arr[pi].cookie = NULL;
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qed_status = 0;
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}
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if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL)
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return -ENOMEM;
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return qed_status;
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p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
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p_sp_sb->pi_info_arr[pi].cookie = NULL;
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return 0;
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}
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u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)
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@ -937,6 +939,39 @@ void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
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}
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}
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static u32 qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u16 sb_id)
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{
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u32 val = qed_rd(p_hwfn, p_ptt,
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IGU_REG_MAPPING_MEMORY +
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sizeof(u32) * sb_id);
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struct qed_igu_block *p_block;
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p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id];
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/* stop scanning when hit first invalid PF entry */
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if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
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GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
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goto out;
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/* Fill the block information */
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p_block->status = QED_IGU_STATUS_VALID;
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p_block->function_id = GET_FIELD(val,
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IGU_MAPPING_LINE_FUNCTION_NUMBER);
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p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
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p_block->vector_number = GET_FIELD(val,
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IGU_MAPPING_LINE_VECTOR_NUMBER);
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DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
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"IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d is_pf = %d vector_num = 0x%x\n",
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sb_id, val, p_block->function_id,
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p_block->is_pf, p_block->vector_number);
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out:
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return val;
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}
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int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt)
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{
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@ -963,26 +998,13 @@ int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
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sb_id++) {
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blk = &p_igu_info->igu_map.igu_blocks[sb_id];
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val = qed_rd(p_hwfn, p_ptt,
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IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id);
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val = qed_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id);
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/* stop scanning when hit first invalid PF entry */
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if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
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GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
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break;
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blk->status = QED_IGU_STATUS_VALID;
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blk->function_id = GET_FIELD(val,
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IGU_MAPPING_LINE_FUNCTION_NUMBER);
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blk->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
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blk->vector_number = GET_FIELD(val,
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IGU_MAPPING_LINE_VECTOR_NUMBER);
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DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
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"IGU_BLOCK[sb_id]:%x:func_id = %d is_pf = %d vector_num = 0x%x\n",
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val, blk->function_id, blk->is_pf,
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blk->vector_number);
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if (blk->is_pf) {
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if (blk->function_id == p_hwfn->rel_pf_id) {
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blk->status |= QED_IGU_STATUS_PF;
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@ -1121,18 +1143,17 @@ void qed_int_setup(struct qed_hwfn *p_hwfn,
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qed_int_sp_dpc_setup(p_hwfn);
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}
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int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
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int *p_iov_blks)
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void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
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struct qed_sb_cnt_info *p_sb_cnt_info)
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{
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struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;
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if (!info)
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return 0;
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if (!info || !p_sb_cnt_info)
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return;
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if (p_iov_blks)
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*p_iov_blks = info->free_blks;
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return info->igu_sb_cnt;
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p_sb_cnt_info->sb_cnt = info->igu_sb_cnt;
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p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov;
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p_sb_cnt_info->sb_free_blk = info->free_blks;
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}
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void qed_int_disable_post_isr_release(struct qed_dev *cdev)
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@ -161,12 +161,12 @@ void qed_int_sp_dpc(unsigned long hwfn_cookie);
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* blocks configured for this funciton in the igu.
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*
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* @param p_hwfn
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* @param p_iov_blks - configured free blks for vfs
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* @param p_sb_cnt_info
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*
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* @return int - number of status blocks configured
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*/
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int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
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int *p_iov_blks);
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void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
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struct qed_sb_cnt_info *p_sb_cnt_info);
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/**
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* @brief qed_int_disable_post_isr_release - performs the cleanup post ISR
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@ -634,15 +634,18 @@ static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
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static int qed_slowpath_setup_int(struct qed_dev *cdev,
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enum qed_int_mode int_mode)
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{
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int rc, i;
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u8 num_vectors = 0;
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struct qed_sb_cnt_info sb_cnt_info;
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int rc;
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int i;
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memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
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cdev->int_params.in.int_mode = int_mode;
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for_each_hwfn(cdev, i)
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num_vectors += qed_int_get_num_sbs(&cdev->hwfns[i], NULL) + 1;
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cdev->int_params.in.num_vectors = num_vectors;
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for_each_hwfn(cdev, i) {
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memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
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qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
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cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt;
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cdev->int_params.in.num_vectors++; /* slowpath */
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}
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/* We want a minimum of one slowpath and one fastpath vector per hwfn */
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cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
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@ -446,6 +446,12 @@ struct qed_eth_stats {
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#define RX_PI 0
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#define TX_PI(tc) (RX_PI + 1 + tc)
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struct qed_sb_cnt_info {
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int sb_cnt;
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int sb_iov_cnt;
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int sb_free_blk;
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};
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static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
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{
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u32 prod = 0;
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