[ARM] 4385/2: ixdp425: NAND support
IXDP425 NAND support (arch specific part). The generic platform driver that is used by ixdp425 platfrom is already in upstream kernel in 2.6.22-rc1. Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Signed-off-by: Ruslan Sushko <rsushko@ru.mvista.com> Signed-off-by: Deepak Saxena <dsaxena@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -15,6 +15,10 @@
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#include <linux/tty.h>
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#include <linux/serial_8250.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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@ -24,6 +28,7 @@
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/delay.h>
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static struct flash_platform_data ixdp425_flash_data = {
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.map_name = "cfi_probe",
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@ -44,6 +49,77 @@ static struct platform_device ixdp425_flash = {
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.resource = &ixdp425_flash_resource,
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};
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#if defined(CONFIG_MTD_NAND_PLATFORM) || \
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defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
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#ifdef CONFIG_MTD_PARTITIONS
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const char *part_probes[] = { "cmdlinepart", NULL };
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static struct mtd_partition ixdp425_partitions[] = {
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{
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.name = "ixp400 NAND FS 0",
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.offset = 0,
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.size = SZ_8M
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}, {
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.name = "ixp400 NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL
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},
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};
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#endif
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static void
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ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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int offset = (int)this->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_NCE) {
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gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW);
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udelay(5);
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} else
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gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH);
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offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
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offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
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this->priv = (void *)offset;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W + offset);
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}
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static struct platform_nand_data ixdp425_flash_nand_data = {
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.chip = {
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.chip_delay = 30,
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.options = NAND_NO_AUTOINCR,
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#ifdef CONFIG_MTD_PARTITIONS
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.part_probe_types = part_probes,
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.partitions = ixdp425_partitions,
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.nr_partitions = ARRAY_SIZE(ixdp425_partitions),
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#endif
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},
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.ctrl = {
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.cmd_ctrl = ixdp425_flash_nand_cmd_ctrl
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}
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};
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static struct resource ixdp425_flash_nand_resource = {
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device ixdp425_flash_nand = {
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.name = "gen_nand",
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.id = -1,
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.dev = {
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.platform_data = &ixdp425_flash_nand_data,
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},
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.num_resources = 1,
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.resource = &ixdp425_flash_nand_resource,
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};
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#endif /* CONFIG_MTD_NAND_PLATFORM */
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static struct ixp4xx_i2c_pins ixdp425_i2c_gpio_pins = {
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.sda_pin = IXDP425_SDA_PIN,
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.scl_pin = IXDP425_SCL_PIN,
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@ -104,6 +180,10 @@ static struct platform_device ixdp425_uart = {
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static struct platform_device *ixdp425_devices[] __initdata = {
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&ixdp425_i2c_controller,
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&ixdp425_flash,
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#if defined(CONFIG_MTD_NAND_PLATFORM) || \
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defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
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&ixdp425_flash_nand,
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#endif
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&ixdp425_uart
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};
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@ -115,6 +195,22 @@ static void __init ixdp425_init(void)
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ixdp425_flash_resource.end =
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IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
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#if defined(CONFIG_MTD_NAND_PLATFORM) || \
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defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
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ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
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ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
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gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT);
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/* Configure expansion bus for NAND Flash */
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*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
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IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */
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IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */
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IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/
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IXP4XX_EXP_BUS_WR_EN |
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IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */
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#endif
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if (cpu_is_ixp43x()) {
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ixdp425_uart.num_resources = 1;
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ixdp425_uart_data[1].flags = 0;
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@ -32,4 +32,8 @@
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#define IXDP425_PCI_INTC_PIN 9
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#define IXDP425_PCI_INTD_PIN 8
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/* NAND Flash pins */
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#define IXDP425_NAND_NCE_PIN 12
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#define IXDP425_NAND_CMD_BYTE 0x01
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#define IXDP425_NAND_ADDR_BYTE 0x02
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