ARC: Code cosmetics (Nothing semantical)
* reduce editor lines taken by pt_regs * ARCompact ISA specific part of TLB Miss handlers clubbed together * cleanup some comments Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
Родитель
fce16bc35a
Коммит
4b06ff35fb
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@ -20,27 +20,17 @@ struct pt_regs {
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/* Real registers */
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long bta; /* bta_l1, bta_l2, erbta */
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long lp_start;
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long lp_end;
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long lp_count;
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long lp_start, lp_end, lp_count;
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long status32; /* status32_l1, status32_l2, erstatus */
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long ret; /* ilink1, ilink2 or eret */
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long blink;
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long fp;
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long r26; /* gp */
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long r12;
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long r11;
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long r10;
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long r9;
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long r8;
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long r7;
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long r6;
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long r5;
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long r4;
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long r3;
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long r2;
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long r1;
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long r0;
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long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0;
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long sp; /* user/kernel sp depending on where we came from */
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long orig_r0;
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@ -70,19 +60,7 @@ struct pt_regs {
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/* Callee saved registers - need to be saved only when you are scheduled out */
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struct callee_regs {
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long r25;
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long r24;
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long r23;
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long r22;
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long r21;
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long r20;
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long r19;
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long r18;
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long r17;
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long r16;
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long r15;
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long r14;
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long r13;
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long r25, r24, r23, r22, r21, r20, r19, r18, r17, r16, r15, r14, r13;
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};
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#define instruction_pointer(regs) ((regs)->ret)
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@ -20,9 +20,9 @@ typedef struct {
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#define __ARCH_SPIN_LOCK_LOCKED { __ARCH_SPIN_LOCK_LOCKED__ }
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/*
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* Unlocked: 0x01_00_00_00
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* Read lock(s): 0x00_FF_00_00 to say 0x01
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* Write lock: 0x0, but only possible if prior value "unlocked" 0x0100_0000
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* Unlocked : 0x0100_0000
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* Read lock(s) : 0x00FF_FFFF to 0x01 (Multiple Readers decrement it)
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* Write lock : 0x0, but only if prior value is "unlocked" 0x0100_0000
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*/
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typedef struct {
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volatile unsigned int counter;
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@ -622,12 +622,12 @@ void flush_icache_range(unsigned long kstart, unsigned long kend)
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/*
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* General purpose helper to make I and D cache lines consistent.
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* @paddr is phy addr of region
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* @vaddr is typically user or kernel vaddr (vmalloc)
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* Howver in one instance, flush_icache_range() by kprobe (for a breakpt in
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* @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
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* However in one instance, when called by kprobe (for a breakpt in
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* builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
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* use a paddr to index the cache (despite VIPT). This is fine since since a
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* built-in kernel page will not have any virtual mappings (not even kernel)
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* kprobe on loadable module is different as it will have kvaddr.
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* builtin kernel page will not have any virtual mappings.
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* kprobe on loadable module will be kernel vaddr.
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*/
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void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len)
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{
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@ -44,17 +44,36 @@
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#include <asm/arcregs.h>
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#include <asm/cache.h>
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#include <asm/processor.h>
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#if (CONFIG_ARC_MMU_VER == 1)
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#include <asm/tlb-mmu1.h>
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#endif
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;--------------------------------------------------------------------------
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; scratch memory to save the registers (r0-r3) used to code TLB refill Handler
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; For details refer to comments before TLBMISS_FREEUP_REGS below
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;-----------------------------------------------------------------
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; ARC700 Exception Handling doesn't auto-switch stack and it only provides
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; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
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;
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; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
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; "global" is used to free-up FIRST core reg to be able to code the rest of
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; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
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; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
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; need to be saved as well by extending the "global" to be 4 words. Hence
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; ".size ex_saved_reg1, 16"
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; [All of this dance is to avoid stack switching for each TLB Miss, since we
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; only need to save only a handful of regs, as opposed to complete reg file]
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;
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; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
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; core reg as it will not be SMP safe.
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; Thus scratch AUX reg is used (and no longer used to cache task PGD).
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; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
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; Epilogue thus has to locate the "per-cpu" storage for regs.
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; To avoid cache line bouncing the per-cpu global is aligned/sized per
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; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
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; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"
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; As simple as that....
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;--------------------------------------------------------------------------
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; scratch memory to save [r0-r3] used to code TLB refill Handler
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ARCFP_DATA ex_saved_reg1
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.align 1 << L1_CACHE_SHIFT ; IMP: Must be Cache Line aligned
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.align 1 << L1_CACHE_SHIFT
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.type ex_saved_reg1, @object
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#ifdef CONFIG_SMP
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.size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
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@ -66,6 +85,44 @@ ex_saved_reg1:
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.zero 16
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#endif
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.macro TLBMISS_FREEUP_REGS
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#ifdef CONFIG_SMP
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sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
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GET_CPU_ID r0 ; get to per cpu scratch mem,
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lsl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
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add r0, @ex_saved_reg1, r0
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#else
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st r0, [@ex_saved_reg1]
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mov_s r0, @ex_saved_reg1
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#endif
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st_s r1, [r0, 4]
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st_s r2, [r0, 8]
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st_s r3, [r0, 12]
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; VERIFY if the ASID in MMU-PID Reg is same as
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; one in Linux data structures
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DBG_ASID_MISMATCH
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.endm
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.macro TLBMISS_RESTORE_REGS
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#ifdef CONFIG_SMP
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GET_CPU_ID r0 ; get to per cpu scratch mem
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lsl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
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add r0, @ex_saved_reg1, r0
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ld_s r3, [r0,12]
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ld_s r2, [r0, 8]
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ld_s r1, [r0, 4]
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lr r0, [ARC_REG_SCRATCH_DATA0]
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#else
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mov_s r0, @ex_saved_reg1
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ld_s r3, [r0,12]
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ld_s r2, [r0, 8]
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ld_s r1, [r0, 4]
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ld_s r0, [r0]
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#endif
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.endm
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;============================================================================
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; Troubleshooting Stuff
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;============================================================================
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@ -191,68 +248,6 @@ ex_saved_reg1:
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#endif
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.endm
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;-----------------------------------------------------------------
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; ARC700 Exception Handling doesn't auto-switch stack and it only provides
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; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
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;
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; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
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; "global" is used to free-up FIRST core reg to be able to code the rest of
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; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
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; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
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; need to be saved as well by extending the "global" to be 4 words. Hence
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; ".size ex_saved_reg1, 16"
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; [All of this dance is to avoid stack switching for each TLB Miss, since we
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; only need to save only a handful of regs, as opposed to complete reg file]
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;
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; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
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; core reg as it will not be SMP safe.
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; Thus scratch AUX reg is used (and no longer used to cache task PGD).
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; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
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; Epilogue thus has to locate the "per-cpu" storage for regs.
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; To avoid cache line bouncing the per-cpu global is aligned/sized per
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; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
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; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"
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; As simple as that....
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.macro TLBMISS_FREEUP_REGS
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#ifdef CONFIG_SMP
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sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
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GET_CPU_ID r0 ; get to per cpu scratch mem,
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lsl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
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add r0, @ex_saved_reg1, r0
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#else
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st r0, [@ex_saved_reg1]
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mov_s r0, @ex_saved_reg1
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#endif
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st_s r1, [r0, 4]
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st_s r2, [r0, 8]
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st_s r3, [r0, 12]
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; VERIFY if the ASID in MMU-PID Reg is same as
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; one in Linux data structures
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DBG_ASID_MISMATCH
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.endm
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;-----------------------------------------------------------------
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.macro TLBMISS_RESTORE_REGS
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#ifdef CONFIG_SMP
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GET_CPU_ID r0 ; get to per cpu scratch mem
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lsl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
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add r0, @ex_saved_reg1, r0
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ld_s r3, [r0,12]
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ld_s r2, [r0, 8]
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ld_s r1, [r0, 4]
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lr r0, [ARC_REG_SCRATCH_DATA0]
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#else
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mov_s r0, @ex_saved_reg1
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ld_s r3, [r0,12]
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ld_s r2, [r0, 8]
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ld_s r1, [r0, 4]
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ld_s r0, [r0]
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#endif
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.endm
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ARCFP_CODE ;Fast Path Code, candidate for ICCM
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