clk: meson-g12a: add video decoder clocks
Add the necessary clock parts for: - VDEC_1: used to feed VDEC_1 - VDEC_HEVC: the "back" part of the VDEC_HEVC block - VDEC_HEVCF: the "front" part of the VDEC_HEVC block In previous SoC generations (GXL, GXBB), there was only one VDEC_HEVC clock, which got split in two parts for G12A. Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190319101138.27520-2-mjourdan@baylibre.com
This commit is contained in:
Maxime Jourdan
Neil Armstrong
Родитель
34775209ba
Коммит
4b0f73055a
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@ -1495,6 +1495,151 @@ static struct clk_regmap g12a_vpu = {
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},
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};
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/* VDEC clocks */
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static const char * const g12a_vdec_parent_names[] = {
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"fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
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"hifi_pll", "gp0_pll",
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};
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static struct clk_regmap g12a_vdec_1_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VDEC_CLK_CNTL,
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.mask = 0x7,
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.shift = 9,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_1_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = g12a_vdec_parent_names,
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.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_vdec_1_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VDEC_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_1_div",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vdec_1_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_vdec_1 = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_VDEC_CLK_CNTL,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "vdec_1",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "vdec_1_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_vdec_hevcf_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.mask = 0x7,
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.shift = 9,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_hevcf_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = g12a_vdec_parent_names,
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.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_vdec_hevcf_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_hevcf_div",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vdec_hevcf_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_vdec_hevcf = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "vdec_hevcf",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "vdec_hevcf_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_vdec_hevc_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.mask = 0x7,
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.shift = 25,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_hevc_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = g12a_vdec_parent_names,
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.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_vdec_hevc_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.shift = 16,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdec_hevc_div",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vdec_hevc_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_vdec_hevc = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_VDEC2_CLK_CNTL,
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.bit_idx = 24,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "vdec_hevc",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "vdec_hevc_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* VAPB Clock */
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static const char * const g12a_vapb_parent_names[] = {
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@ -2615,6 +2760,15 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
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[CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
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[CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
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[CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
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[CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
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[CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
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[CLKID_VDEC_1] = &g12a_vdec_1.hw,
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[CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
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[CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
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[CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
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[CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
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[CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
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[CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -2803,6 +2957,15 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
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&g12a_cpu_clk_trace,
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&g12a_pcie_pll_od,
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&g12a_pcie_pll_dco,
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&g12a_vdec_1_sel,
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&g12a_vdec_1_div,
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&g12a_vdec_1,
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&g12a_vdec_hevc_sel,
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&g12a_vdec_hevc_div,
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&g12a_vdec_hevc,
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&g12a_vdec_hevcf_sel,
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&g12a_vdec_hevcf_div,
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&g12a_vdec_hevcf,
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};
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static const struct meson_eeclkc_data g12a_clkc_data = {
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@ -189,8 +189,14 @@
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#define CLKID_PCIE_PLL_DCO 198
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#define CLKID_PCIE_PLL_DCO_DIV2 199
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#define CLKID_PCIE_PLL_OD 200
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#define CLKID_VDEC_1_SEL 202
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#define CLKID_VDEC_1_DIV 203
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#define CLKID_VDEC_HEVC_SEL 205
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#define CLKID_VDEC_HEVC_DIV 206
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#define CLKID_VDEC_HEVCF_SEL 208
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#define CLKID_VDEC_HEVCF_DIV 209
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#define NR_CLKS 202
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#define NR_CLKS 211
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/g12a-clkc.h>
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