ARM: ux500: cut some platform data
This platform data is revoked: the drivers are getting the DMA configuration from the device tree, it has been done like that since the DMA support was merged and this data has not been used since. The remaining auxdata is also unused. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Linus Walleij
Arnd Bergmann
Родитель
1564dd1d2f
Коммит
4b483ed0be
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@ -1,77 +0,0 @@
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/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/gpio.h>
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#include <linux/platform_data/dma-ste-dma40.h>
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#include <linux/platform_data/asoc-ux500-msp.h>
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#include "ste-dma40-db8500.h"
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#include "board-mop500.h"
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static struct stedma40_chan_cfg msp0_dma_rx = {
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.high_priority = true,
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.dir = DMA_DEV_TO_MEM,
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.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
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};
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static struct stedma40_chan_cfg msp0_dma_tx = {
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.high_priority = true,
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.dir = DMA_MEM_TO_DEV,
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.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
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};
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struct msp_i2s_platform_data msp0_platform_data = {
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.id = 0,
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.msp_i2s_dma_rx = &msp0_dma_rx,
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.msp_i2s_dma_tx = &msp0_dma_tx,
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};
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static struct stedma40_chan_cfg msp1_dma_rx = {
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.high_priority = true,
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.dir = DMA_DEV_TO_MEM,
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.dev_type = DB8500_DMA_DEV30_MSP3,
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};
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static struct stedma40_chan_cfg msp1_dma_tx = {
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.high_priority = true,
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.dir = DMA_MEM_TO_DEV,
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.dev_type = DB8500_DMA_DEV30_MSP1,
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};
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struct msp_i2s_platform_data msp1_platform_data = {
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.id = 1,
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.msp_i2s_dma_rx = NULL,
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.msp_i2s_dma_tx = &msp1_dma_tx,
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};
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static struct stedma40_chan_cfg msp2_dma_rx = {
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.high_priority = true,
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.dir = DMA_DEV_TO_MEM,
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.dev_type = DB8500_DMA_DEV14_MSP2,
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};
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static struct stedma40_chan_cfg msp2_dma_tx = {
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.high_priority = true,
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.dir = DMA_MEM_TO_DEV,
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.dev_type = DB8500_DMA_DEV14_MSP2,
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.use_fixed_channel = true,
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.phy_channel = 1,
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};
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struct msp_i2s_platform_data msp2_platform_data = {
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.id = 2,
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.msp_i2s_dma_rx = &msp2_dma_rx,
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.msp_i2s_dma_tx = &msp2_dma_tx,
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};
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struct msp_i2s_platform_data msp3_platform_data = {
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.id = 3,
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.msp_i2s_dma_rx = &msp1_dma_rx,
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.msp_i2s_dma_tx = NULL,
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};
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@ -1,17 +0,0 @@
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/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef __BOARD_MOP500_H
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#define __BOARD_MOP500_H
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#include <linux/platform_data/asoc-ux500-msp.h>
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extern struct msp_i2s_platform_data msp0_platform_data;
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extern struct msp_i2s_platform_data msp1_platform_data;
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extern struct msp_i2s_platform_data msp2_platform_data;
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extern struct msp_i2s_platform_data msp3_platform_data;
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#endif
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@ -33,7 +33,6 @@
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#include "setup.h"
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#include "board-mop500.h"
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#include "db8500-regs.h"
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static int __init ux500_l2x0_unlock(void)
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@ -141,21 +140,6 @@ static struct arm_pmu_platdata db8500_pmu_platdata = {
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static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
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/* Requires call-back bindings. */
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OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
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/* Requires DMA bindings. */
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OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
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"ux500-msp-i2s.0", &msp0_platform_data),
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OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
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"ux500-msp-i2s.1", &msp1_platform_data),
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OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
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"ux500-msp-i2s.2", &msp2_platform_data),
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OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
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"ux500-msp-i2s.3", &msp3_platform_data),
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/* Requires non-DT:able platform data. */
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OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", NULL),
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OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL),
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OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
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OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
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NULL),
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{},
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};
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@ -1,85 +0,0 @@
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/*
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* arch/arm/mach-ux500/ste_dma40_db8500.h
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* DB8500-SoC-specific configuration for DMA40
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*
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* Copyright (C) ST-Ericsson 2007-2010
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* License terms: GNU General Public License (GPL) version 2
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* Author: Per Friden <per.friden@stericsson.com>
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
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*/
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#ifndef STE_DMA40_DB8500_H
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#define STE_DMA40_DB8500_H
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#define DB8500_DMA_NR_DEV 64
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/*
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* Unless otherwise specified, all channels numbers are used for
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* TX & RX, and can be used for either source or destination
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* channels.
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*/
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enum dma_dev_type {
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DB8500_DMA_DEV0_SPI0 = 0,
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DB8500_DMA_DEV1_SD_MMC0 = 1,
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DB8500_DMA_DEV2_SD_MMC1 = 2,
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DB8500_DMA_DEV3_SD_MMC2 = 3,
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DB8500_DMA_DEV4_I2C1 = 4,
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DB8500_DMA_DEV5_I2C3 = 5,
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DB8500_DMA_DEV6_I2C2 = 6,
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DB8500_DMA_DEV7_I2C4 = 7, /* Only on V1 and later */
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DB8500_DMA_DEV8_SSP0 = 8,
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DB8500_DMA_DEV9_SSP1 = 9,
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DB8500_DMA_DEV10_MCDE_RX = 10, /* RX only */
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DB8500_DMA_DEV11_UART2 = 11,
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DB8500_DMA_DEV12_UART1 = 12,
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DB8500_DMA_DEV13_UART0 = 13,
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DB8500_DMA_DEV14_MSP2 = 14,
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DB8500_DMA_DEV15_I2C0 = 15,
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DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15 = 16,
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DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14 = 17,
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DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13 = 18,
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DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12 = 19,
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DB8500_DMA_DEV20_SLIM0_CH0_HSI_CH0 = 20,
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DB8500_DMA_DEV21_SLIM0_CH1_HSI_CH1 = 21,
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DB8500_DMA_DEV22_SLIM0_CH2_HSI_CH2 = 22,
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DB8500_DMA_DEV23_SLIM0_CH3_HSI_CH3 = 23,
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DB8500_DMA_DEV24_SXA0 = 24,
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DB8500_DMA_DEV25_SXA1 = 25,
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DB8500_DMA_DEV26_SXA2 = 26,
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DB8500_DMA_DEV27_SXA3 = 27,
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DB8500_DMA_DEV28_SD_MM2 = 28,
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DB8500_DMA_DEV29_SD_MM0 = 29,
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DB8500_DMA_DEV30_MSP1 = 30,
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/* On DB8500v2, MSP3 RX replaces MSP1 RX */
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DB8500_DMA_DEV30_MSP3 = 30,
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DB8500_DMA_DEV31_MSP0_SLIM0_CH0 = 31,
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DB8500_DMA_DEV32_SD_MM1 = 32,
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DB8500_DMA_DEV33_SPI2 = 33,
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DB8500_DMA_DEV34_I2C3_RX2_TX2 = 34,
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DB8500_DMA_DEV35_SPI1 = 35,
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DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11 = 36,
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DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10 = 37,
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DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9 = 38,
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DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 = 39,
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DB8500_DMA_DEV40_SPI3 = 40,
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DB8500_DMA_DEV41_SD_MM3 = 41,
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DB8500_DMA_DEV42_SD_MM4 = 42,
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DB8500_DMA_DEV43_SD_MM5 = 43,
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DB8500_DMA_DEV44_SXA4 = 44,
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DB8500_DMA_DEV45_SXA5 = 45,
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DB8500_DMA_DEV46_SLIM0_CH8_SRC_SXA6 = 46,
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DB8500_DMA_DEV47_SLIM0_CH9_SRC_SXA7 = 47,
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DB8500_DMA_DEV48_CAC1 = 48,
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DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49, /* TX only */
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DB8500_DMA_DEV50_HAC1_TX = 50, /* TX only */
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DB8500_DMA_MEMCPY_TX_0 = 51, /* TX only */
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DB8500_DMA_DEV52_SLIM0_CH4_HSI_CH4 = 52,
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DB8500_DMA_DEV53_SLIM0_CH5_HSI_CH5 = 53,
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DB8500_DMA_DEV54_SLIM0_CH6_HSI_CH6 = 54,
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DB8500_DMA_DEV55_SLIM0_CH7_HSI_CH7 = 55,
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/* 56 -> 60 are channels reserved for memcpy only */
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DB8500_DMA_DEV61_CAC0 = 61,
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DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62, /* TX only */
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DB8500_DMA_DEV63_HAC0_TX = 63, /* TX only */
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};
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#endif
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