pinctrl/rockchip: always enable clock for gpio controller
Since gate and ungate pclk of gpio has very litte benifit for system power consumption, just keep it always ungate. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210816011948.1118959-2-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Jianqun Xu
Linus Walleij
Родитель
e73f0f0ee7
Коммит
4b522bbf80
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@ -2299,17 +2299,8 @@ static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
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u32 data;
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int ret;
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ret = clk_enable(bank->clk);
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if (ret < 0) {
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dev_err(bank->drvdata->dev,
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"failed to enable clock for bank %s\n", bank->name);
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return ret;
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}
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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clk_disable(bank->clk);
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if (data & BIT(offset))
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return GPIO_LINE_DIRECTION_OUT;
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@ -2335,7 +2326,6 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
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if (ret < 0)
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return ret;
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clk_enable(bank->clk);
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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@ -2347,7 +2337,6 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
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writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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clk_disable(bank->clk);
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return 0;
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}
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@ -2798,7 +2787,6 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
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unsigned long flags;
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u32 data;
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clk_enable(bank->clk);
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl(reg);
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@ -2808,7 +2796,6 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
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writel(data, reg);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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clk_disable(bank->clk);
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}
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/*
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@ -2820,9 +2807,7 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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u32 data;
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clk_enable(bank->clk);
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data = readl(bank->reg_base + GPIO_EXT_PORT);
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clk_disable(bank->clk);
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data >>= offset;
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data &= 1;
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return data;
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@ -2858,7 +2843,6 @@ static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
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unsigned long flags;
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u32 data;
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clk_enable(bank->clk);
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl(reg);
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@ -2869,7 +2853,6 @@ static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
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writel(data, reg);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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clk_disable(bank->clk);
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}
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/*
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@ -2914,9 +2897,7 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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if (!bank->domain)
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return -ENXIO;
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clk_enable(bank->clk);
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virq = irq_create_mapping(bank->domain, offset);
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clk_disable(bank->clk);
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return (virq) ? : -ENXIO;
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}
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@ -3015,7 +2996,6 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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if (ret < 0)
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return ret;
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clk_enable(bank->clk);
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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@ -3073,7 +3053,6 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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default:
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irq_gc_unlock(gc);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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clk_disable(bank->clk);
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return -EINVAL;
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}
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@ -3082,7 +3061,6 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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irq_gc_unlock(gc);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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clk_disable(bank->clk);
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return 0;
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}
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@ -3092,10 +3070,8 @@ static void rockchip_irq_suspend(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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clk_enable(bank->clk);
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bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
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irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
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clk_disable(bank->clk);
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}
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static void rockchip_irq_resume(struct irq_data *d)
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@ -3103,9 +3079,7 @@ static void rockchip_irq_resume(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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clk_enable(bank->clk);
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irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
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clk_disable(bank->clk);
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}
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static void rockchip_irq_enable(struct irq_data *d)
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@ -3113,7 +3087,6 @@ static void rockchip_irq_enable(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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clk_enable(bank->clk);
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irq_gc_mask_clr_bit(d);
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}
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@ -3123,7 +3096,6 @@ static void rockchip_irq_disable(struct irq_data *d)
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struct rockchip_pin_bank *bank = gc->private;
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irq_gc_mask_set_bit(d);
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clk_disable(bank->clk);
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}
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static int rockchip_interrupts_register(struct platform_device *pdev,
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@ -3143,19 +3115,11 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
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continue;
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}
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ret = clk_enable(bank->clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
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bank->name);
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continue;
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}
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bank->domain = irq_domain_add_linear(bank->of_node, 32,
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&irq_generic_chip_ops, NULL);
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if (!bank->domain) {
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dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
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bank->name);
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clk_disable(bank->clk);
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continue;
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}
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@ -3166,7 +3130,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
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dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
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bank->name);
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irq_domain_remove(bank->domain);
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clk_disable(bank->clk);
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continue;
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}
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@ -3198,7 +3161,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
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irq_set_chained_handler_and_data(bank->irq,
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rockchip_irq_demux, bank);
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clk_disable(bank->clk);
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}
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return 0;
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@ -3317,7 +3279,7 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
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if (IS_ERR(bank->clk))
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return PTR_ERR(bank->clk);
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return clk_prepare(bank->clk);
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return clk_prepare_enable(bank->clk);
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}
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static const struct of_device_id rockchip_pinctrl_dt_match[];
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