sh: math-emu support
This implements initial math-emu support, aimed primarily at SH-3. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Takashi YOSHII
Paul Mundt
Родитель
317a6104a9
Коммит
4b565680d1
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@ -339,6 +339,15 @@ config SH_FPU
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This option must be set in order to enable the FPU.
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config SH_FPU_EMU
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bool "FPU emulation support"
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depends on !SH_FPU && EXPERIMENTAL
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default n
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help
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Selecting this option will enable support for software FPU emulation.
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Most SH-3 users will want to say Y here, whereas most SH-4 users will
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want to say N.
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config SH_DSP
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bool "DSP support"
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depends on !CPU_SH4
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@ -79,6 +79,7 @@ head-y := arch/sh/kernel/head.o arch/sh/kernel/init_task.o
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LIBGCC := $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
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core-y += arch/sh/kernel/ arch/sh/mm/
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core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
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# Boards
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machdir-$(CONFIG_SH_SOLUTION_ENGINE) := se/770x
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@ -38,38 +38,13 @@
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#include <asm/kgdb.h>
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#define CHK_REMOTE_DEBUG(regs) \
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{ \
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if ((kgdb_debug_hook != (kgdb_debug_hook_t *) NULL) && (!user_mode(regs))) \
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{ \
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if (kgdb_debug_hook && !user_mode(regs))\
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(*kgdb_debug_hook)(regs); \
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} \
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}
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#else
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#define CHK_REMOTE_DEBUG(regs)
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#endif
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#define DO_ERROR(trapnr, signr, str, name, tsk) \
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asmlinkage void do_##name(unsigned long r4, unsigned long r5, \
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unsigned long r6, unsigned long r7, \
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struct pt_regs regs) \
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{ \
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unsigned long error_code; \
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\
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/* Check if it's a DSP instruction */ \
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if (is_dsp_inst(®s)) { \
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/* Enable DSP mode, and restart instruction. */ \
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regs.sr |= SR_DSP; \
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return; \
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} \
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\
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asm volatile("stc r2_bank, %0": "=r" (error_code)); \
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local_irq_enable(); \
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tsk->thread.error_code = error_code; \
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tsk->thread.trap_no = trapnr; \
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CHK_REMOTE_DEBUG(®s); \
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force_sig(signr, tsk); \
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die_if_no_fixup(str,®s,error_code); \
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}
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#ifdef CONFIG_CPU_SH2
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#define TRAP_RESERVED_INST 4
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#define TRAP_ILLEGAL_SLOT_INST 6
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@ -575,8 +550,117 @@ int is_dsp_inst(struct pt_regs *regs)
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#define is_dsp_inst(regs) (0)
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#endif /* CONFIG_SH_DSP */
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DO_ERROR(TRAP_RESERVED_INST, SIGILL, "reserved instruction", reserved_inst, current)
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DO_ERROR(TRAP_ILLEGAL_SLOT_INST, SIGILL, "illegal slot instruction", illegal_slot_inst, current)
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extern int do_fpu_inst(unsigned short, struct pt_regs*);
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asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7,
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struct pt_regs regs)
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{
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unsigned long error_code;
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struct task_struct *tsk = current;
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#ifdef CONFIG_SH_FPU_EMU
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unsigned short inst;
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int err;
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get_user(inst, (unsigned short*)regs.pc);
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err = do_fpu_inst(inst, ®s);
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if (!err) {
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regs.pc += 2;
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return;
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}
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/* not a FPU inst. */
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#endif
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#ifdef CONFIG_SH_DSP
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/* Check if it's a DSP instruction */
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if (is_dsp_inst(®s)) {
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/* Enable DSP mode, and restart instruction. */
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regs.sr |= SR_DSP;
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return;
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}
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#endif
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asm volatile("stc r2_bank, %0": "=r" (error_code));
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local_irq_enable();
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tsk->thread.error_code = error_code;
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tsk->thread.trap_no = TRAP_RESERVED_INST;
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CHK_REMOTE_DEBUG(®s);
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force_sig(SIGILL, tsk);
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die_if_no_fixup("reserved instruction", ®s, error_code);
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}
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#ifdef CONFIG_SH_FPU_EMU
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static int emulate_branch(unsigned short inst, struct pt_regs* regs)
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{
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/*
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* bfs: 8fxx: PC+=d*2+4;
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* bts: 8dxx: PC+=d*2+4;
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* bra: axxx: PC+=D*2+4;
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* bsr: bxxx: PC+=D*2+4 after PR=PC+4;
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* braf:0x23: PC+=Rn*2+4;
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* bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
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* jmp: 4x2b: PC=Rn;
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* jsr: 4x0b: PC=Rn after PR=PC+4;
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* rts: 000b: PC=PR;
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*/
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if ((inst & 0xfd00) == 0x8d00) {
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regs->pc += SH_PC_8BIT_OFFSET(inst);
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return 0;
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}
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if ((inst & 0xe000) == 0xa000) {
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regs->pc += SH_PC_12BIT_OFFSET(inst);
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return 0;
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}
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if ((inst & 0xf0df) == 0x0003) {
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regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
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return 0;
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}
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if ((inst & 0xf0df) == 0x400b) {
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regs->pc = regs->regs[(inst & 0x0f00) >> 8];
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return 0;
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}
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if ((inst & 0xffff) == 0x000b) {
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regs->pc = regs->pr;
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return 0;
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}
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return 1;
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}
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#endif
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asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7,
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struct pt_regs regs)
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{
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unsigned long error_code;
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struct task_struct *tsk = current;
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#ifdef CONFIG_SH_FPU_EMU
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unsigned short inst;
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get_user(inst, (unsigned short *)regs.pc + 1);
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if (!do_fpu_inst(inst, ®s)) {
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get_user(inst, (unsigned short *)regs.pc);
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if (!emulate_branch(inst, ®s))
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return;
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/* fault in branch.*/
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}
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/* not a FPU inst. */
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#endif
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asm volatile("stc r2_bank, %0": "=r" (error_code));
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local_irq_enable();
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tsk->thread.error_code = error_code;
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tsk->thread.trap_no = TRAP_RESERVED_INST;
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CHK_REMOTE_DEBUG(®s);
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force_sig(SIGILL, tsk);
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die_if_no_fixup("illegal slot instruction", ®s, error_code);
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}
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asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7,
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@ -634,14 +718,16 @@ void __init trap_init(void)
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exception_handling_table[TRAP_ILLEGAL_SLOT_INST]
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= (void *)do_illegal_slot_inst;
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#ifdef CONFIG_CPU_SH4
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if (!(cpu_data->flags & CPU_HAS_FPU)) {
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/* For SH-4 lacking an FPU, treat floating point instructions
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as reserved. */
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#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
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defined(CONFIG_SH_FPU_EMU)
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/*
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* For SH-4 lacking an FPU, treat floating point instructions as
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* reserved. They'll be handled in the math-emu case, or faulted on
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* otherwise.
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*/
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/* entry 64 corresponds to EXPEVT=0x800 */
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exception_handling_table[64] = (void *)do_reserved_inst;
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exception_handling_table[65] = (void *)do_illegal_slot_inst;
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}
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#endif
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/* Setup VBR for boot cpu */
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@ -0,0 +1 @@
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obj-y := math.o
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@ -0,0 +1,624 @@
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/*
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* arch/sh/math-emu/math.c
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*
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* Copyright (C) 2006 Takashi YOSHII <takasi-y@ops.dti.ne.jp>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <asm/system.h>
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#include <asm/uaccess.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "sfp-util.h"
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#include <math-emu/soft-fp.h>
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#include <math-emu/single.h>
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#include <math-emu/double.h>
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#define FPUL (fregs->fpul)
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#define FPSCR (fregs->fpscr)
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#define FPSCR_RM (FPSCR&3)
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#define FPSCR_DN ((FPSCR>>18)&1)
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#define FPSCR_PR ((FPSCR>>19)&1)
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#define FPSCR_SZ ((FPSCR>>20)&1)
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#define FPSCR_FR ((FPSCR>>21)&1)
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#define FPSCR_MASK 0x003fffffUL
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#define BANK(n) (n^(FPSCR_FR?16:0))
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#define FR ((unsigned long*)(fregs->fp_regs))
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#define FR0 (FR[BANK(0)])
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#define FRn (FR[BANK(n)])
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#define FRm (FR[BANK(m)])
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#define DR ((unsigned long long*)(fregs->fp_regs))
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#define DRn (DR[BANK(n)/2])
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#define DRm (DR[BANK(m)/2])
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#define XREG(n) (n^16)
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#define XFn (FR[BANK(XREG(n))])
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#define XFm (FR[BANK(XREG(m))])
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#define XDn (DR[BANK(XREG(n))/2])
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#define XDm (DR[BANK(XREG(m))/2])
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#define R0 (regs->regs[0])
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#define Rn (regs->regs[n])
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#define Rm (regs->regs[m])
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#define WRITE(d,a) ({if(put_user(d, (typeof (d)*)a)) return -EFAULT;})
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#define READ(d,a) ({if(get_user(d, (typeof (d)*)a)) return -EFAULT;})
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#define PACK_S(r,f) FP_PACK_SP(&r,f)
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#define UNPACK_S(f,r) FP_UNPACK_SP(f,&r)
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#define PACK_D(r,f) \
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{u32 t[2]; FP_PACK_DP(t,f); ((u32*)&r)[0]=t[1]; ((u32*)&r)[1]=t[0];}
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#define UNPACK_D(f,r) \
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{u32 t[2]; t[0]=((u32*)&r)[1]; t[1]=((u32*)&r)[0]; FP_UNPACK_DP(f,t);}
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// 2 args instructions.
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#define BOTH_PRmn(op,x) \
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FP_DECL_EX; if(FPSCR_PR) op(D,x,DRm,DRn); else op(S,x,FRm,FRn);
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#define CMP_X(SZ,R,M,N) do{ \
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FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); \
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UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
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FP_CMP_##SZ(R, Fn, Fm, 2); }while(0)
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#define EQ_X(SZ,R,M,N) do{ \
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FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); \
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UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
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FP_CMP_EQ_##SZ(R, Fn, Fm); }while(0)
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#define CMP(OP) ({ int r; BOTH_PRmn(OP##_X,r); r; })
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static int
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fcmp_gt(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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if (CMP(CMP) > 0)
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regs->sr |= 1;
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else
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regs->sr &= ~1;
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return 0;
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}
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static int
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fcmp_eq(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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if (CMP(CMP /*EQ*/) == 0)
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regs->sr |= 1;
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else
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regs->sr &= ~1;
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return 0;
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}
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#define ARITH_X(SZ,OP,M,N) do{ \
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FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); FP_DECL_##SZ(Fr); \
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UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
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FP_##OP##_##SZ(Fr, Fn, Fm); \
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PACK_##SZ(N, Fr); }while(0)
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static int
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fadd(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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BOTH_PRmn(ARITH_X, ADD);
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return 0;
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}
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static int
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fsub(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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BOTH_PRmn(ARITH_X, SUB);
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return 0;
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}
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static int
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fmul(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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BOTH_PRmn(ARITH_X, MUL);
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return 0;
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}
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static int
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fdiv(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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BOTH_PRmn(ARITH_X, DIV);
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return 0;
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}
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static int
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fmac(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
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{
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FP_DECL_EX;
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FP_DECL_S(Fr);
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FP_DECL_S(Ft);
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FP_DECL_S(F0);
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FP_DECL_S(Fm);
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FP_DECL_S(Fn);
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UNPACK_S(F0, FR0);
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UNPACK_S(Fm, FRm);
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UNPACK_S(Fn, FRn);
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FP_MUL_S(Ft, Fm, F0);
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FP_ADD_S(Fr, Fn, Ft);
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PACK_S(FRn, Fr);
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return 0;
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}
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// to process fmov's extention (odd n for DR access XD).
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#define FMOV_EXT(x) if(x&1) x+=16-1
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static int
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fmov_idx_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(n);
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READ(FRn, Rm + R0 + 4);
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n++;
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READ(FRn, Rm + R0);
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} else {
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READ(FRn, Rm + R0);
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}
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return 0;
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}
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static int
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fmov_mem_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(n);
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READ(FRn, Rm + 4);
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n++;
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READ(FRn, Rm);
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} else {
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READ(FRn, Rm);
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}
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return 0;
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}
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static int
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fmov_inc_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(n);
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READ(FRn, Rm + 4);
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n++;
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READ(FRn, Rm);
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Rm += 8;
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} else {
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READ(FRn, Rm);
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Rm += 4;
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}
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return 0;
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}
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static int
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fmov_reg_idx(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(m);
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WRITE(FRm, Rn + R0 + 4);
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m++;
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WRITE(FRm, Rn + R0);
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} else {
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WRITE(FRm, Rn + R0);
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}
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return 0;
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}
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static int
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fmov_reg_mem(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
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int n)
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{
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if (FPSCR_SZ) {
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FMOV_EXT(m);
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WRITE(FRm, Rn + 4);
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m++;
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WRITE(FRm, Rn);
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} else {
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WRITE(FRm, Rn);
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}
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return 0;
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}
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static int
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fmov_reg_dec(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
|
||||
int n)
|
||||
{
|
||||
if (FPSCR_SZ) {
|
||||
FMOV_EXT(m);
|
||||
Rn -= 8;
|
||||
WRITE(FRm, Rn + 4);
|
||||
m++;
|
||||
WRITE(FRm, Rn);
|
||||
} else {
|
||||
Rn -= 4;
|
||||
WRITE(FRm, Rn);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
fmov_reg_reg(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m,
|
||||
int n)
|
||||
{
|
||||
if (FPSCR_SZ) {
|
||||
FMOV_EXT(m);
|
||||
FMOV_EXT(n);
|
||||
DRn = DRm;
|
||||
} else {
|
||||
FRn = FRm;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
fnop_mn(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
// 1 arg instructions.
|
||||
#define NOTYETn(i) static int i(struct sh_fpu_soft_struct *fregs, int n) \
|
||||
{ printk( #i " not yet done.\n"); return 0; }
|
||||
|
||||
NOTYETn(ftrv)
|
||||
NOTYETn(fsqrt)
|
||||
NOTYETn(fipr)
|
||||
NOTYETn(fsca)
|
||||
NOTYETn(fsrra)
|
||||
|
||||
#define EMU_FLOAT_X(SZ,N) do { \
|
||||
FP_DECL_##SZ(Fn); \
|
||||
FP_FROM_INT_##SZ(Fn, FPUL, 32, int); \
|
||||
PACK_##SZ(N, Fn); }while(0)
|
||||
static int ffloat(struct sh_fpu_soft_struct *fregs, int n)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
|
||||
if (FPSCR_PR)
|
||||
EMU_FLOAT_X(D, DRn);
|
||||
else
|
||||
EMU_FLOAT_X(S, FRn);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define EMU_FTRC_X(SZ,N) do { \
|
||||
FP_DECL_##SZ(Fn); \
|
||||
UNPACK_##SZ(Fn, N); \
|
||||
FP_TO_INT_##SZ(FPUL, Fn, 32, 1); }while(0)
|
||||
static int ftrc(struct sh_fpu_soft_struct *fregs, int n)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
|
||||
if (FPSCR_PR)
|
||||
EMU_FTRC_X(D, DRn);
|
||||
else
|
||||
EMU_FTRC_X(S, FRn);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fcnvsd(struct sh_fpu_soft_struct *fregs, int n)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_S(Fn);
|
||||
FP_DECL_D(Fr);
|
||||
UNPACK_S(Fn, FPUL);
|
||||
FP_CONV(D, S, 2, 1, Fr, Fn);
|
||||
PACK_D(DRn, Fr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fcnvds(struct sh_fpu_soft_struct *fregs, int n)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_D(Fn);
|
||||
FP_DECL_S(Fr);
|
||||
UNPACK_D(Fn, DRn);
|
||||
FP_CONV(S, D, 1, 2, Fr, Fn);
|
||||
PACK_S(FPUL, Fr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fxchg(struct sh_fpu_soft_struct *fregs, int flag)
|
||||
{
|
||||
FPSCR ^= flag;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsts(struct sh_fpu_soft_struct *fregs, int n)
|
||||
{
|
||||
FRn = FPUL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int flds(struct sh_fpu_soft_struct *fregs, int n)
|
||||
{
|
||||
FPUL = FRn;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fneg(struct sh_fpu_soft_struct *fregs, int n)
|
||||
{
|
||||
FRn ^= (1 << (_FP_W_TYPE_SIZE - 1));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fabs(struct sh_fpu_soft_struct *fregs, int n)
|
||||
{
|
||||
FRn &= ~(1 << (_FP_W_TYPE_SIZE - 1));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fld0(struct sh_fpu_soft_struct *fregs, int n)
|
||||
{
|
||||
FRn = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fld1(struct sh_fpu_soft_struct *fregs, int n)
|
||||
{
|
||||
FRn = (_FP_EXPBIAS_S << (_FP_FRACBITS_S - 1));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fnop_n(struct sh_fpu_soft_struct *fregs, int n)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/// Instruction decoders.
|
||||
|
||||
static int id_fxfd(struct sh_fpu_soft_struct *, int);
|
||||
static int id_fnxd(struct sh_fpu_soft_struct *, struct pt_regs *, int, int);
|
||||
|
||||
static int (*fnxd[])(struct sh_fpu_soft_struct *, int) = {
|
||||
fsts, flds, ffloat, ftrc, fneg, fabs, fsqrt, fsrra,
|
||||
fld0, fld1, fcnvsd, fcnvds, fnop_n, fnop_n, fipr, id_fxfd
|
||||
};
|
||||
|
||||
static int (*fnmx[])(struct sh_fpu_soft_struct *, struct pt_regs *, int, int) = {
|
||||
fadd, fsub, fmul, fdiv, fcmp_eq, fcmp_gt, fmov_idx_reg, fmov_reg_idx,
|
||||
fmov_mem_reg, fmov_inc_reg, fmov_reg_mem, fmov_reg_dec,
|
||||
fmov_reg_reg, id_fnxd, fmac, fnop_mn};
|
||||
|
||||
static int id_fxfd(struct sh_fpu_soft_struct *fregs, int x)
|
||||
{
|
||||
const int flag[] = { FPSCR_SZ, FPSCR_PR, FPSCR_FR, 0 };
|
||||
switch (x & 3) {
|
||||
case 3:
|
||||
fxchg(fregs, flag[x >> 2]);
|
||||
break;
|
||||
case 1:
|
||||
ftrv(fregs, x - 1);
|
||||
break;
|
||||
default:
|
||||
fsca(fregs, x);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
id_fnxd(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int x, int n)
|
||||
{
|
||||
return (fnxd[x])(fregs, n);
|
||||
}
|
||||
|
||||
static int
|
||||
id_fnmx(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, u16 code)
|
||||
{
|
||||
int n = (code >> 8) & 0xf, m = (code >> 4) & 0xf, x = code & 0xf;
|
||||
return (fnmx[x])(fregs, regs, m, n);
|
||||
}
|
||||
|
||||
static int
|
||||
id_sys(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, u16 code)
|
||||
{
|
||||
int n = ((code >> 8) & 0xf);
|
||||
unsigned long *reg = (code & 0x0010) ? &FPUL : &FPSCR;
|
||||
|
||||
switch (code & 0xf0ff) {
|
||||
case 0x005a:
|
||||
case 0x006a:
|
||||
Rn = *reg;
|
||||
break;
|
||||
case 0x405a:
|
||||
case 0x406a:
|
||||
*reg = Rn;
|
||||
break;
|
||||
case 0x4052:
|
||||
case 0x4062:
|
||||
Rn -= 4;
|
||||
WRITE(*reg, Rn);
|
||||
break;
|
||||
case 0x4056:
|
||||
case 0x4066:
|
||||
READ(*reg, Rn);
|
||||
Rn += 4;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fpu_emulate(u16 code, struct sh_fpu_soft_struct *fregs, struct pt_regs *regs)
|
||||
{
|
||||
if ((code & 0xf000) == 0xf000)
|
||||
return id_fnmx(fregs, regs, code);
|
||||
else
|
||||
return id_sys(fregs, regs, code);
|
||||
}
|
||||
|
||||
/**
|
||||
* denormal_to_double - Given denormalized float number,
|
||||
* store double float
|
||||
*
|
||||
* @fpu: Pointer to sh_fpu_hard structure
|
||||
* @n: Index to FP register
|
||||
*/
|
||||
static void denormal_to_double(struct sh_fpu_hard_struct *fpu, int n)
|
||||
{
|
||||
unsigned long du, dl;
|
||||
unsigned long x = fpu->fpul;
|
||||
int exp = 1023 - 126;
|
||||
|
||||
if (x != 0 && (x & 0x7f800000) == 0) {
|
||||
du = (x & 0x80000000);
|
||||
while ((x & 0x00800000) == 0) {
|
||||
x <<= 1;
|
||||
exp--;
|
||||
}
|
||||
x &= 0x007fffff;
|
||||
du |= (exp << 20) | (x >> 3);
|
||||
dl = x << 29;
|
||||
|
||||
fpu->fp_regs[n] = du;
|
||||
fpu->fp_regs[n+1] = dl;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* ieee_fpe_handler - Handle denormalized number exception
|
||||
*
|
||||
* @regs: Pointer to register structure
|
||||
*
|
||||
* Returns 1 when it's handled (should not cause exception).
|
||||
*/
|
||||
static int ieee_fpe_handler(struct pt_regs *regs)
|
||||
{
|
||||
unsigned short insn = *(unsigned short *)regs->pc;
|
||||
unsigned short finsn;
|
||||
unsigned long nextpc;
|
||||
int nib[4] = {
|
||||
(insn >> 12) & 0xf,
|
||||
(insn >> 8) & 0xf,
|
||||
(insn >> 4) & 0xf,
|
||||
insn & 0xf};
|
||||
|
||||
if (nib[0] == 0xb ||
|
||||
(nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb)) /* bsr & jsr */
|
||||
regs->pr = regs->pc + 4;
|
||||
|
||||
if (nib[0] == 0xa || nib[0] == 0xb) { /* bra & bsr */
|
||||
nextpc = regs->pc + 4 + ((short) ((insn & 0xfff) << 4) >> 3);
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x8 && nib[1] == 0xd) { /* bt/s */
|
||||
if (regs->sr & 1)
|
||||
nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
|
||||
else
|
||||
nextpc = regs->pc + 4;
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x8 && nib[1] == 0xf) { /* bf/s */
|
||||
if (regs->sr & 1)
|
||||
nextpc = regs->pc + 4;
|
||||
else
|
||||
nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x4 && nib[3] == 0xb &&
|
||||
(nib[2] == 0x0 || nib[2] == 0x2)) { /* jmp & jsr */
|
||||
nextpc = regs->regs[nib[1]];
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x0 && nib[3] == 0x3 &&
|
||||
(nib[2] == 0x0 || nib[2] == 0x2)) { /* braf & bsrf */
|
||||
nextpc = regs->pc + 4 + regs->regs[nib[1]];
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (insn == 0x000b) { /* rts */
|
||||
nextpc = regs->pr;
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else {
|
||||
nextpc = regs->pc + 2;
|
||||
finsn = insn;
|
||||
}
|
||||
|
||||
if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
|
||||
struct task_struct *tsk = current;
|
||||
|
||||
if ((tsk->thread.fpu.hard.fpscr & (1 << 17))) {
|
||||
/* FPU error */
|
||||
denormal_to_double (&tsk->thread.fpu.hard,
|
||||
(finsn >> 8) & 0xf);
|
||||
tsk->thread.fpu.hard.fpscr &=
|
||||
~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
|
||||
set_tsk_thread_flag(tsk, TIF_USEDFPU);
|
||||
} else {
|
||||
tsk->thread.trap_no = 11;
|
||||
tsk->thread.error_code = 0;
|
||||
force_sig(SIGFPE, tsk);
|
||||
}
|
||||
|
||||
regs->pc = nextpc;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
asmlinkage void do_fpu_error(unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7,
|
||||
struct pt_regs regs)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
|
||||
if (ieee_fpe_handler (®s))
|
||||
return;
|
||||
|
||||
regs.pc += 2;
|
||||
tsk->thread.trap_no = 11;
|
||||
tsk->thread.error_code = 0;
|
||||
force_sig(SIGFPE, tsk);
|
||||
}
|
||||
|
||||
/**
|
||||
* fpu_init - Initialize FPU registers
|
||||
* @fpu: Pointer to software emulated FPU registers.
|
||||
*/
|
||||
static void fpu_init(struct sh_fpu_soft_struct *fpu)
|
||||
{
|
||||
int i;
|
||||
|
||||
fpu->fpscr = FPSCR_INIT;
|
||||
fpu->fpul = 0;
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
fpu->fp_regs[i] = 0;
|
||||
fpu->xfp_regs[i]= 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* do_fpu_inst - Handle reserved instructions for FPU emulation
|
||||
* @inst: instruction code.
|
||||
* @regs: registers on stack.
|
||||
*/
|
||||
int do_fpu_inst(unsigned short inst, struct pt_regs *regs)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
struct sh_fpu_soft_struct *fpu = &(tsk->thread.fpu.soft);
|
||||
|
||||
if (!test_tsk_thread_flag(tsk, TIF_USEDFPU)) {
|
||||
/* initialize once. */
|
||||
fpu_init(fpu);
|
||||
set_tsk_thread_flag(tsk, TIF_USEDFPU);
|
||||
}
|
||||
|
||||
return fpu_emulate(inst, fpu, regs);
|
||||
}
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* These are copied from glibc/stdlib/longlong.h
|
||||
*/
|
||||
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
do { \
|
||||
UWtype __x; \
|
||||
__x = (al) + (bl); \
|
||||
(sh) = (ah) + (bh) + (__x < (al)); \
|
||||
(sl) = __x; \
|
||||
} while (0)
|
||||
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
do { \
|
||||
UWtype __x; \
|
||||
__x = (al) - (bl); \
|
||||
(sh) = (ah) - (bh) - (__x > (al)); \
|
||||
(sl) = __x; \
|
||||
} while (0)
|
||||
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
|
||||
: "=r" ((u32)(w1)), "=r" ((u32)(w0)) \
|
||||
: "r" ((u32)(u)), "r" ((u32)(v)) \
|
||||
: "macl", "mach")
|
||||
|
||||
#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
|
||||
#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
|
||||
#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
|
||||
|
||||
#define udiv_qrnnd(q, r, n1, n0, d) \
|
||||
do { \
|
||||
UWtype __d1, __d0, __q1, __q0; \
|
||||
UWtype __r1, __r0, __m; \
|
||||
__d1 = __ll_highpart (d); \
|
||||
__d0 = __ll_lowpart (d); \
|
||||
\
|
||||
__r1 = (n1) % __d1; \
|
||||
__q1 = (n1) / __d1; \
|
||||
__m = (UWtype) __q1 * __d0; \
|
||||
__r1 = __r1 * __ll_B | __ll_highpart (n0); \
|
||||
if (__r1 < __m) \
|
||||
{ \
|
||||
__q1--, __r1 += (d); \
|
||||
if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
|
||||
if (__r1 < __m) \
|
||||
__q1--, __r1 += (d); \
|
||||
} \
|
||||
__r1 -= __m; \
|
||||
\
|
||||
__r0 = __r1 % __d1; \
|
||||
__q0 = __r1 / __d1; \
|
||||
__m = (UWtype) __q0 * __d0; \
|
||||
__r0 = __r0 * __ll_B | __ll_lowpart (n0); \
|
||||
if (__r0 < __m) \
|
||||
{ \
|
||||
__q0--, __r0 += (d); \
|
||||
if (__r0 >= (d)) \
|
||||
if (__r0 < __m) \
|
||||
__q0--, __r0 += (d); \
|
||||
} \
|
||||
__r0 -= __m; \
|
||||
\
|
||||
(q) = (UWtype) __q1 * __ll_B | __q0; \
|
||||
(r) = __r0; \
|
||||
} while (0)
|
||||
|
||||
#define abort() return 0
|
||||
|
||||
#define __BYTE_ORDER __LITTLE_ENDIAN
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/* Machine-dependent software floating-point definitions.
|
||||
SuperH kernel version.
|
||||
Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
|
||||
This file is part of the GNU C Library.
|
||||
Contributed by Richard Henderson (rth@cygnus.com),
|
||||
Jakub Jelinek (jj@ultra.linux.cz),
|
||||
David S. Miller (davem@redhat.com) and
|
||||
Peter Maydell (pmaydell@chiark.greenend.org.uk).
|
||||
|
||||
The GNU C Library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Library General Public License as
|
||||
published by the Free Software Foundation; either version 2 of the
|
||||
License, or (at your option) any later version.
|
||||
|
||||
The GNU C Library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Library General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Library General Public
|
||||
License along with the GNU C Library; see the file COPYING.LIB. If
|
||||
not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#ifndef _SFP_MACHINE_H
|
||||
#define _SFP_MACHINE_H
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
#define _FP_W_TYPE_SIZE 32
|
||||
#define _FP_W_TYPE unsigned long
|
||||
#define _FP_WS_TYPE signed long
|
||||
#define _FP_I_TYPE long
|
||||
|
||||
#define _FP_MUL_MEAT_S(R,X,Y) \
|
||||
_FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
|
||||
#define _FP_MUL_MEAT_D(R,X,Y) \
|
||||
_FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
|
||||
#define _FP_MUL_MEAT_Q(R,X,Y) \
|
||||
_FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
|
||||
|
||||
#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y)
|
||||
#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
|
||||
#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
|
||||
|
||||
#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
|
||||
#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
|
||||
#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
|
||||
#define _FP_NANSIGN_S 0
|
||||
#define _FP_NANSIGN_D 0
|
||||
#define _FP_NANSIGN_Q 0
|
||||
|
||||
#define _FP_KEEPNANFRACP 1
|
||||
|
||||
/*
|
||||
* If one NaN is signaling and the other is not,
|
||||
* we choose that one, otherwise we choose X.
|
||||
*/
|
||||
#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
|
||||
do { \
|
||||
if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
|
||||
&& !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \
|
||||
{ \
|
||||
R##_s = Y##_s; \
|
||||
_FP_FRAC_COPY_##wc(R,Y); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
R##_s = X##_s; \
|
||||
_FP_FRAC_COPY_##wc(R,X); \
|
||||
} \
|
||||
R##_c = FP_CLS_NAN; \
|
||||
} while (0)
|
||||
|
||||
//#define FP_ROUNDMODE FPSCR_RM
|
||||
#define FP_DENORM_ZERO 1/*FPSCR_DN*/
|
||||
|
||||
/* Exception flags. */
|
||||
#define FP_EX_INVALID (1<<4)
|
||||
#define FP_EX_DIVZERO (1<<3)
|
||||
#define FP_EX_OVERFLOW (1<<2)
|
||||
#define FP_EX_UNDERFLOW (1<<1)
|
||||
#define FP_EX_INEXACT (1<<0)
|
||||
|
||||
#endif
|
||||
|
||||
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