i2c-davinci: Fix race when setting up for TX
When setting up to transmit, a race exists between the ISR and i2c_davinci_xfer_msg() trying to load the first byte and adjust counters. This is mostly visible for transmits > 1 byte long. The hardware starts sending immediately that MDR is loaded. IMR trickery doesn't work because if we start sending, finish the first byte and an XRDY event occurs before we load IMR to unmask it, we never get an interrupt, and we timeout. Move the MDR load after DXR,IMR loads to avoid this race without locking. Tested on DM355 connected to Techwell TW2836 and Wolfson WM8985 Signed-off-by: Jon Povey <jon.povey@racelogic.co.uk> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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cc33e54290
Коммит
4bba0fd8d1
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@ -357,9 +357,6 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
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dev->terminate = 0;
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dev->terminate = 0;
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/* write the data into mode register */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
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/*
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/*
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* First byte should be set here, not after interrupt,
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* First byte should be set here, not after interrupt,
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* because transmit-data-ready interrupt can come before
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* because transmit-data-ready interrupt can come before
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@ -371,6 +368,9 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
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dev->buf_len--;
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dev->buf_len--;
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}
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}
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/* write the data into mode register; start transmitting */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
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r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
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r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
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dev->adapter.timeout);
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dev->adapter.timeout);
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if (r == 0) {
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if (r == 0) {
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