Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband: IB/mlx4: Fix MTT leakage in resize CQ IB/ehca: Fix problem with generated flush work completions IB/ehca: Change misleading error message on memory hotplug mlx4_core: Save/restore default port IB capability mask
This commit is contained in:
Коммит
4bc2a9bf8c
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@ -163,7 +163,8 @@ struct ehca_mod_qp_parm {
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/* struct for tracking if cqes have been reported to the application */
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struct ehca_qmap_entry {
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u16 app_wr_id;
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u16 reported;
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u8 reported;
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u8 cqe_req;
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};
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struct ehca_queue_map {
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@ -171,6 +172,7 @@ struct ehca_queue_map {
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unsigned int entries;
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unsigned int tail;
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unsigned int left_to_poll;
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unsigned int next_wqe_idx; /* Idx to first wqe to be flushed */
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};
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struct ehca_qp {
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@ -994,8 +994,7 @@ static int ehca_mem_notifier(struct notifier_block *nb,
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if (printk_timed_ratelimit(&ehca_dmem_warn_time,
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30 * 1000))
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ehca_gen_err("DMEM operations are not allowed"
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"as long as an ehca adapter is"
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"attached to the LPAR");
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"in conjunction with eHCA");
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return NOTIFY_BAD;
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}
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}
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@ -435,9 +435,13 @@ static void reset_queue_map(struct ehca_queue_map *qmap)
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{
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int i;
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qmap->tail = 0;
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for (i = 0; i < qmap->entries; i++)
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qmap->tail = qmap->entries - 1;
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qmap->left_to_poll = 0;
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qmap->next_wqe_idx = 0;
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for (i = 0; i < qmap->entries; i++) {
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qmap->map[i].reported = 1;
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qmap->map[i].cqe_req = 0;
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}
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}
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/*
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@ -1121,6 +1125,7 @@ static int calc_left_cqes(u64 wqe_p, struct ipz_queue *ipz_queue,
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void *wqe_v;
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u64 q_ofs;
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u32 wqe_idx;
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unsigned int tail_idx;
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/* convert real to abs address */
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wqe_p = wqe_p & (~(1UL << 63));
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@ -1133,12 +1138,17 @@ static int calc_left_cqes(u64 wqe_p, struct ipz_queue *ipz_queue,
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return -EFAULT;
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}
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tail_idx = (qmap->tail + 1) % qmap->entries;
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wqe_idx = q_ofs / ipz_queue->qe_size;
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if (wqe_idx < qmap->tail)
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qmap->left_to_poll = (qmap->entries - qmap->tail) + wqe_idx;
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else
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qmap->left_to_poll = wqe_idx - qmap->tail;
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/* check all processed wqes, whether a cqe is requested or not */
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while (tail_idx != wqe_idx) {
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if (qmap->map[tail_idx].cqe_req)
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qmap->left_to_poll++;
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tail_idx = (tail_idx + 1) % qmap->entries;
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}
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/* save index in queue, where we have to start flushing */
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qmap->next_wqe_idx = wqe_idx;
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return 0;
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}
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@ -1185,10 +1195,14 @@ static int check_for_left_cqes(struct ehca_qp *my_qp, struct ehca_shca *shca)
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} else {
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spin_lock_irqsave(&my_qp->send_cq->spinlock, flags);
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my_qp->sq_map.left_to_poll = 0;
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my_qp->sq_map.next_wqe_idx = (my_qp->sq_map.tail + 1) %
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my_qp->sq_map.entries;
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spin_unlock_irqrestore(&my_qp->send_cq->spinlock, flags);
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spin_lock_irqsave(&my_qp->recv_cq->spinlock, flags);
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my_qp->rq_map.left_to_poll = 0;
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my_qp->rq_map.next_wqe_idx = (my_qp->rq_map.tail + 1) %
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my_qp->rq_map.entries;
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spin_unlock_irqrestore(&my_qp->recv_cq->spinlock, flags);
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}
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@ -179,6 +179,7 @@ static inline int ehca_write_swqe(struct ehca_qp *qp,
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qmap_entry->app_wr_id = get_app_wr_id(send_wr->wr_id);
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qmap_entry->reported = 0;
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qmap_entry->cqe_req = 0;
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switch (send_wr->opcode) {
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case IB_WR_SEND:
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@ -203,8 +204,10 @@ static inline int ehca_write_swqe(struct ehca_qp *qp,
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if ((send_wr->send_flags & IB_SEND_SIGNALED ||
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qp->init_attr.sq_sig_type == IB_SIGNAL_ALL_WR)
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&& !hidden)
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&& !hidden) {
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wqe_p->wr_flag |= WQE_WRFLAG_REQ_SIGNAL_COM;
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qmap_entry->cqe_req = 1;
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}
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if (send_wr->opcode == IB_WR_SEND_WITH_IMM ||
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send_wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) {
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@ -569,6 +572,7 @@ static int internal_post_recv(struct ehca_qp *my_qp,
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qmap_entry = &my_qp->rq_map.map[rq_map_idx];
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qmap_entry->app_wr_id = get_app_wr_id(cur_recv_wr->wr_id);
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qmap_entry->reported = 0;
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qmap_entry->cqe_req = 1;
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wqe_cnt++;
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} /* eof for cur_recv_wr */
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@ -706,19 +710,6 @@ repoll:
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goto repoll;
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wc->qp = &my_qp->ib_qp;
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if (is_error) {
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/*
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* set left_to_poll to 0 because in error state, we will not
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* get any additional CQEs
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*/
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ehca_add_to_err_list(my_qp, 1);
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my_qp->sq_map.left_to_poll = 0;
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if (HAS_RQ(my_qp))
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ehca_add_to_err_list(my_qp, 0);
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my_qp->rq_map.left_to_poll = 0;
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}
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qmap_tail_idx = get_app_wr_id(cqe->work_request_id);
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if (!(cqe->w_completion_flags & WC_SEND_RECEIVE_BIT))
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/* We got a send completion. */
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@ -727,6 +718,26 @@ repoll:
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/* We got a receive completion. */
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qmap = &my_qp->rq_map;
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/* advance the tail pointer */
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qmap->tail = qmap_tail_idx;
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if (is_error) {
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/*
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* set left_to_poll to 0 because in error state, we will not
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* get any additional CQEs
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*/
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my_qp->sq_map.next_wqe_idx = (my_qp->sq_map.tail + 1) %
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my_qp->sq_map.entries;
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my_qp->sq_map.left_to_poll = 0;
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ehca_add_to_err_list(my_qp, 1);
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my_qp->rq_map.next_wqe_idx = (my_qp->rq_map.tail + 1) %
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my_qp->rq_map.entries;
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my_qp->rq_map.left_to_poll = 0;
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if (HAS_RQ(my_qp))
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ehca_add_to_err_list(my_qp, 0);
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}
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qmap_entry = &qmap->map[qmap_tail_idx];
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if (qmap_entry->reported) {
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ehca_warn(cq->device, "Double cqe on qp_num=%#x",
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@ -738,10 +749,6 @@ repoll:
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wc->wr_id = replace_wr_id(cqe->work_request_id, qmap_entry->app_wr_id);
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qmap_entry->reported = 1;
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/* this is a proper completion, we need to advance the tail pointer */
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if (++qmap->tail == qmap->entries)
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qmap->tail = 0;
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/* if left_to_poll is decremented to 0, add the QP to the error list */
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if (qmap->left_to_poll > 0) {
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qmap->left_to_poll--;
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@ -805,13 +812,14 @@ static int generate_flush_cqes(struct ehca_qp *my_qp, struct ib_cq *cq,
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else
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qmap = &my_qp->rq_map;
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qmap_entry = &qmap->map[qmap->tail];
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qmap_entry = &qmap->map[qmap->next_wqe_idx];
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while ((nr < num_entries) && (qmap_entry->reported == 0)) {
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/* generate flush CQE */
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memset(wc, 0, sizeof(*wc));
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offset = qmap->tail * ipz_queue->qe_size;
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offset = qmap->next_wqe_idx * ipz_queue->qe_size;
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wqe = (struct ehca_wqe *)ipz_qeit_calc(ipz_queue, offset);
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if (!wqe) {
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ehca_err(cq->device, "Invalid wqe offset=%#lx on "
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@ -850,11 +858,12 @@ static int generate_flush_cqes(struct ehca_qp *my_qp, struct ib_cq *cq,
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wc->qp = &my_qp->ib_qp;
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/* mark as reported and advance tail pointer */
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/* mark as reported and advance next_wqe pointer */
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qmap_entry->reported = 1;
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if (++qmap->tail == qmap->entries)
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qmap->tail = 0;
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qmap_entry = &qmap->map[qmap->tail];
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qmap->next_wqe_idx++;
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if (qmap->next_wqe_idx == qmap->entries)
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qmap->next_wqe_idx = 0;
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qmap_entry = &qmap->map[qmap->next_wqe_idx];
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wc++; nr++;
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}
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@ -343,6 +343,7 @@ int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
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{
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struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
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struct mlx4_ib_cq *cq = to_mcq(ibcq);
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struct mlx4_mtt mtt;
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int outst_cqe;
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int err;
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@ -376,10 +377,13 @@ int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
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goto out;
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}
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mtt = cq->buf.mtt;
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err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
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if (err)
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goto err_buf;
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mlx4_mtt_cleanup(dev->dev, &mtt);
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if (ibcq->uobject) {
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cq->buf = cq->resize_buf->buf;
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cq->ibcq.cqe = cq->resize_buf->cqe;
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@ -406,6 +410,7 @@ int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
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goto out;
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err_buf:
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mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
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if (!ibcq->uobject)
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mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
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cq->resize_buf->cqe);
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@ -753,6 +753,7 @@ static int mlx4_setup_hca(struct mlx4_dev *dev)
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struct mlx4_priv *priv = mlx4_priv(dev);
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int err;
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int port;
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__be32 ib_port_default_caps;
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err = mlx4_init_uar_table(dev);
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if (err) {
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@ -852,6 +853,13 @@ static int mlx4_setup_hca(struct mlx4_dev *dev)
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}
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for (port = 1; port <= dev->caps.num_ports; port++) {
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ib_port_default_caps = 0;
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err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
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if (err)
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mlx4_warn(dev, "failed to get port %d default "
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"ib capabilities (%d). Continuing with "
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"caps = 0\n", port, err);
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dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
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err = mlx4_SET_PORT(dev, port);
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if (err) {
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mlx4_err(dev, "Failed to set port %d, aborting\n",
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@ -385,5 +385,6 @@ void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
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void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
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int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
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int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
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#endif /* MLX4_H */
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@ -258,6 +258,42 @@ out:
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}
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EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
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int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
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{
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struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
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u8 *inbuf, *outbuf;
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int err;
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inmailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(inmailbox))
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return PTR_ERR(inmailbox);
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outmailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(outmailbox)) {
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mlx4_free_cmd_mailbox(dev, inmailbox);
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return PTR_ERR(outmailbox);
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}
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inbuf = inmailbox->buf;
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outbuf = outmailbox->buf;
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memset(inbuf, 0, 256);
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memset(outbuf, 0, 256);
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inbuf[0] = 1;
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inbuf[1] = 1;
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inbuf[2] = 1;
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inbuf[3] = 1;
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*(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
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*(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
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err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
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MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C);
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if (!err)
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*caps = *(__be32 *) (outbuf + 84);
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mlx4_free_cmd_mailbox(dev, inmailbox);
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mlx4_free_cmd_mailbox(dev, outmailbox);
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return err;
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}
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int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port)
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{
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struct mlx4_cmd_mailbox *mailbox;
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@ -273,7 +309,8 @@ int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port)
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((u8 *) mailbox->buf)[3] = 6;
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((__be16 *) mailbox->buf)[4] = cpu_to_be16(1 << 15);
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((__be16 *) mailbox->buf)[6] = cpu_to_be16(1 << 15);
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}
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} else
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((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
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err = mlx4_cmd(dev, mailbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
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MLX4_CMD_TIME_CLASS_B);
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@ -179,6 +179,7 @@ struct mlx4_caps {
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int num_ports;
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int vl_cap[MLX4_MAX_PORTS + 1];
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int ib_mtu_cap[MLX4_MAX_PORTS + 1];
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__be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
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u64 def_mac[MLX4_MAX_PORTS + 1];
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int eth_mtu_cap[MLX4_MAX_PORTS + 1];
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int gid_table_len[MLX4_MAX_PORTS + 1];
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