arm64: Check for selected granule support
Ensure that the selected page size is supported by the CPU(s). If it doesn't park it. Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -44,6 +44,26 @@
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#define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\
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(!!x)<<8 | 0x1f)
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#define ID_AA64MMFR0_TGRAN4_SHIFT 28
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#define ID_AA64MMFR0_TGRAN64_SHIFT 24
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#define ID_AA64MMFR0_TGRAN16_SHIFT 20
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#define ID_AA64MMFR0_TGRAN4_NI 0xf
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#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
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#define ID_AA64MMFR0_TGRAN64_NI 0xf
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#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
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#define ID_AA64MMFR0_TGRAN16_NI 0x0
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#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
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#if defined(CONFIG_ARM64_4K_PAGES)
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#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
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#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
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#elif defined(CONFIG_ARM64_64K_PAGES)
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#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
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#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
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#endif
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#ifdef __ASSEMBLY__
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.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
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@ -31,10 +31,11 @@
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#include <asm/cputype.h>
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#include <asm/kernel-pgtable.h>
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#include <asm/memory.h>
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#include <asm/thread_info.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/sysreg.h>
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#include <asm/thread_info.h>
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#include <asm/virt.h>
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#define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
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@ -613,10 +614,17 @@ ENDPROC(__secondary_switched)
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* x0 = SCTLR_EL1 value for turning on the MMU.
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* x27 = *virtual* address to jump to upon completion
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*
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* other registers depend on the function called upon completion
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* Other registers depend on the function called upon completion.
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*
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* Checks if the selected granule size is supported by the CPU.
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* If it isn't, park the CPU
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*/
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.section ".idmap.text", "ax"
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__enable_mmu:
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mrs x1, ID_AA64MMFR0_EL1
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ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4
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cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
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b.ne __no_granule_support
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ldr x5, =vectors
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msr vbar_el1, x5
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msr ttbr0_el1, x25 // load TTBR0
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@ -634,3 +642,8 @@ __enable_mmu:
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isb
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br x27
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ENDPROC(__enable_mmu)
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__no_granule_support:
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wfe
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b __no_granule_support
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ENDPROC(__no_granule_support)
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