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ARM: imx6: Align ssi nodes between mx6 variants 

Since commit 98ea6ad2ed (ARM: dts: imx6: use imx51-ssi) the mx6 ssi is
compatible with imx51, so align all the mx6 variant ssi compatible strings as:

compatible = "fsl,<imx6-soc>-ssi", "fsl,imx51-ssi";

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This commit is contained in:
Fabio Estevam 2014-07-07 10:04:52 -03:00 коммит произвёл Shawn Guo
Родитель ea336fa8ee
Коммит 4c03527eb7
3 изменённых файлов: 9 добавлений и 15 удалений
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9
arch/arm/boot/dts/imx6qdl.dtsi
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@ -274,8 +274,7 @@
ssi1: ssi@02028000 {
compatible = "fsl,imx6q-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
"fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SSI1_IPG>;
@ -288,8 +287,7 @@
ssi2: ssi@0202c000 {
compatible = "fsl,imx6q-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
"fsl,imx51-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SSI2_IPG>;
@ -302,8 +300,7 @@
ssi3: ssi@02030000 {
compatible = "fsl,imx6q-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
"fsl,imx51-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SSI3_IPG>;

9
arch/arm/boot/dts/imx6sl.dtsi
Просмотреть файл

@ -227,8 +227,7 @@
ssi1: ssi@02028000 {
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
"fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI1>;
@ -241,8 +240,7 @@
ssi2: ssi@0202c000 {
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
"fsl,imx51-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI2>;
@ -255,8 +253,7 @@
ssi3: ssi@02030000 {
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
"fsl,imx51-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI3>;

6
arch/arm/boot/dts/imx6sx.dtsi
Просмотреть файл

@ -298,7 +298,7 @@
};
ssi1: ssi@02028000 {
compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
@ -311,7 +311,7 @@
};
ssi2: ssi@0202c000 {
compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
@ -324,7 +324,7 @@
};
ssi3: ssi@02030000 {
compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
reg = <0x02030000 0x4000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_SSI3_IPG>,