iommu/vt-d: Convert IR set_affinity function to remap_ops
The function to set interrupt affinity with interrupt remapping enabled is Intel specific too. So move it to the irq_remap_ops too. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Acked-by: Yinghai Lu <yinghai@kernel.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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@ -40,6 +40,9 @@ extern int intr_setup_ioapic_entry(int irq,
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struct IO_APIC_route_entry *entry,
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unsigned int destination, int vector,
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struct io_apic_irq_attr *attr);
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extern int intr_set_affinity(struct irq_data *data,
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const struct cpumask *mask,
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bool force);
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#else /* CONFIG_IRQ_REMAP */
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@ -59,6 +62,12 @@ static inline int intr_setup_ioapic_entry(int irq,
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{
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return -ENODEV;
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}
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static inline int intr_set_affinity(struct irq_data *data,
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const struct cpumask *mask,
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bool force)
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{
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return 0;
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}
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#endif /* CONFIG_IRQ_REMAP */
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#endif /* __X86_INTR_REMAPPING_H */
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@ -2327,71 +2327,6 @@ ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
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return ret;
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}
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#ifdef CONFIG_IRQ_REMAP
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/*
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* Migrate the IO-APIC irq in the presence of intr-remapping.
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*
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* For both level and edge triggered, irq migration is a simple atomic
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* update(of vector and cpu destination) of IRTE and flush the hardware cache.
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*
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* For level triggered, we eliminate the io-apic RTE modification (with the
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* updated vector information), by using a virtual vector (io-apic pin number).
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* Real vector that is used for interrupting cpu will be coming from
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* the interrupt-remapping table entry.
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*
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* As the migration is a simple atomic update of IRTE, the same mechanism
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* is used to migrate MSI irq's in the presence of interrupt-remapping.
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*/
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static int
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ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force)
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{
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struct irq_cfg *cfg = data->chip_data;
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unsigned int dest, irq = data->irq;
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struct irte irte;
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if (!cpumask_intersects(mask, cpu_online_mask))
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return -EINVAL;
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if (get_irte(irq, &irte))
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return -EBUSY;
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if (assign_irq_vector(irq, cfg, mask))
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return -EBUSY;
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dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
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irte.vector = cfg->vector;
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irte.dest_id = IRTE_DEST(dest);
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/*
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* Atomically updates the IRTE with the new destination, vector
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* and flushes the interrupt entry cache.
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*/
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modify_irte(irq, &irte);
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/*
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* After this point, all the interrupts will start arriving
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* at the new destination. So, time to cleanup the previous
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* vector allocation.
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*/
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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cpumask_copy(data->affinity, mask);
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return 0;
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}
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#else
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static inline int
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ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force)
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{
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return 0;
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}
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#endif
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asmlinkage void smp_irq_move_cleanup_interrupt(void)
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{
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unsigned vector, me;
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@ -2636,7 +2571,7 @@ static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
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chip->irq_eoi = ir_ack_apic_level;
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#ifdef CONFIG_SMP
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chip->irq_set_affinity = ir_ioapic_set_affinity;
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chip->irq_set_affinity = intr_set_affinity;
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#endif
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}
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#endif /* CONFIG_IRQ_REMAP */
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@ -3826,7 +3761,7 @@ void __init setup_ioapic_dest(void)
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mask = apic->target_cpus();
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if (intr_remapping_enabled)
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ir_ioapic_set_affinity(idata, mask, false);
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intr_set_affinity(idata, mask, false);
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else
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ioapic_set_affinity(idata, mask, false);
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}
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@ -901,6 +901,59 @@ static int intel_setup_ioapic_entry(int irq,
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return 0;
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}
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/*
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* Migrate the IO-APIC irq in the presence of intr-remapping.
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*
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* For both level and edge triggered, irq migration is a simple atomic
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* update(of vector and cpu destination) of IRTE and flush the hardware cache.
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*
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* For level triggered, we eliminate the io-apic RTE modification (with the
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* updated vector information), by using a virtual vector (io-apic pin number).
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* Real vector that is used for interrupting cpu will be coming from
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* the interrupt-remapping table entry.
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*
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* As the migration is a simple atomic update of IRTE, the same mechanism
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* is used to migrate MSI irq's in the presence of interrupt-remapping.
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*/
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static int
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intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force)
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{
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struct irq_cfg *cfg = data->chip_data;
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unsigned int dest, irq = data->irq;
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struct irte irte;
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if (!cpumask_intersects(mask, cpu_online_mask))
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return -EINVAL;
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if (get_irte(irq, &irte))
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return -EBUSY;
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if (assign_irq_vector(irq, cfg, mask))
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return -EBUSY;
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dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
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irte.vector = cfg->vector;
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irte.dest_id = IRTE_DEST(dest);
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/*
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* Atomically updates the IRTE with the new destination, vector
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* and flushes the interrupt entry cache.
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*/
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modify_irte(irq, &irte);
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/*
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* After this point, all the interrupts will start arriving
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* at the new destination. So, time to cleanup the previous
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* vector allocation.
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*/
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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cpumask_copy(data->affinity, mask);
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return 0;
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}
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struct irq_remap_ops intel_irq_remap_ops = {
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.supported = intel_intr_remapping_supported,
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@ -910,4 +963,5 @@ struct irq_remap_ops intel_irq_remap_ops = {
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.hardware_reenable = reenable_intr_remapping,
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.enable_faulting = enable_drhd_fault_handling,
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.setup_ioapic_entry = intel_setup_ioapic_entry,
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.set_affinity = intel_ioapic_set_affinity,
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};
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@ -110,3 +110,12 @@ int intr_setup_ioapic_entry(int irq,
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return remap_ops->setup_ioapic_entry(irq, entry, destination,
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vector, attr);
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}
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int intr_set_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force)
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{
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if (!remap_ops || !remap_ops->set_affinity)
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return 0;
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return remap_ops->set_affinity(data, mask, force);
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}
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@ -26,6 +26,8 @@
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struct IO_APIC_route_entry;
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struct io_apic_irq_attr;
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struct irq_data;
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struct cpumask;
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extern int disable_intremap;
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extern int disable_sourceid_checking;
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@ -54,6 +56,10 @@ struct irq_remap_ops {
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int (*setup_ioapic_entry)(int irq, struct IO_APIC_route_entry *,
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unsigned int, int,
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struct io_apic_irq_attr *);
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/* Set the CPU affinity of a remapped interrupt */
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int (*set_affinity)(struct irq_data *data, const struct cpumask *mask,
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bool force);
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};
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extern struct irq_remap_ops intel_irq_remap_ops;
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