spi_mpc8xxx: Add support for QE DMA mode and CPM1/CPM2 chips
This patch adds QE buffer descriptors mode support for the spi_mpc8xxx driver, and as a side effect we now support CPM1 and CPM2 SPI controllers. That means that today we support almost all MPC SPI controllers: - MPC834x-style controllers (support PIO mode only); - CPM1 and CPM2 controllers (support DMA mode only); - QE SPI controllers in CPU mode (PIO mode with shift quirks); - QE SPI controllers in buffer descriptors (DMA) mode; The only controller we don't currently support is a newer eSPI (with a dedicated chip selects and a bit different registers map). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Anton Vorontsov
Kumar Gala
Родитель
87ec0e98cf
Коммит
4c1fba4429
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@ -147,9 +147,6 @@ config SPI_MPC8xxx
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This enables using the Freescale MPC8xxx SPI controllers in master
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mode.
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This driver uses a simple set of shift registers for data (opposed
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to the CPM based descriptor model).
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config SPI_OMAP_UWIRE
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tristate "OMAP1 MicroWire"
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depends on ARCH_OMAP1
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@ -5,6 +5,10 @@
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*
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* Copyright (C) 2006 Polycom, Inc.
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*
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* CPM SPI and QE buffer descriptors mode support:
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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@ -27,6 +31,9 @@
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#include <linux/spi/spi_bitbang.h>
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#include <linux/platform_device.h>
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#include <linux/fsl_devices.h>
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#include <linux/dma-mapping.h>
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#include <linux/mm.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/gpio.h>
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@ -34,8 +41,19 @@
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#include <linux/of_spi.h>
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#include <sysdev/fsl_soc.h>
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#include <asm/cpm.h>
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#include <asm/qe.h>
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#include <asm/irq.h>
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/* CPM1 and CPM2 are mutually exclusive. */
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#ifdef CONFIG_CPM1
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#include <asm/cpm1.h>
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#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
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#else
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#include <asm/cpm2.h>
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#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
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#endif
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/* SPI Controller registers */
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struct mpc8xxx_spi_reg {
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u8 res1[0x20];
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@ -47,6 +65,28 @@ struct mpc8xxx_spi_reg {
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__be32 receive;
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};
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/* SPI Parameter RAM */
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struct spi_pram {
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__be16 rbase; /* Rx Buffer descriptor base address */
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__be16 tbase; /* Tx Buffer descriptor base address */
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u8 rfcr; /* Rx function code */
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u8 tfcr; /* Tx function code */
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__be16 mrblr; /* Max receive buffer length */
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__be32 rstate; /* Internal */
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__be32 rdp; /* Internal */
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__be16 rbptr; /* Internal */
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__be16 rbc; /* Internal */
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__be32 rxtmp; /* Internal */
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__be32 tstate; /* Internal */
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__be32 tdp; /* Internal */
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__be16 tbptr; /* Internal */
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__be16 tbc; /* Internal */
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__be32 txtmp; /* Internal */
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__be32 res; /* Tx temp. */
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__be16 rpbase; /* Relocation pointer (CPM1 only) */
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__be16 res1; /* Reserved */
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};
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/* SPI Controller mode register definitions */
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#define SPMODE_LOOP (1 << 30)
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#define SPMODE_CI_INACTIVEHIGH (1 << 29)
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@ -75,14 +115,40 @@ struct mpc8xxx_spi_reg {
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#define SPIM_NE 0x00000200 /* Not empty */
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#define SPIM_NF 0x00000100 /* Not full */
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#define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
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#define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
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/* SPCOM register values */
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#define SPCOM_STR (1 << 23) /* Start transmit */
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#define SPI_PRAM_SIZE 0x100
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#define SPI_MRBLR ((unsigned int)PAGE_SIZE)
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/* SPI Controller driver's private data. */
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struct mpc8xxx_spi {
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struct device *dev;
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struct mpc8xxx_spi_reg __iomem *base;
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/* rx & tx bufs from the spi_transfer */
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const void *tx;
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void *rx;
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int subblock;
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struct spi_pram __iomem *pram;
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struct cpm_buf_desc __iomem *tx_bd;
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struct cpm_buf_desc __iomem *rx_bd;
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struct spi_transfer *xfer_in_progress;
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/* dma addresses for CPM transfers */
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dma_addr_t tx_dma;
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dma_addr_t rx_dma;
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bool map_tx_dma;
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bool map_rx_dma;
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dma_addr_t dma_dummy_tx;
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dma_addr_t dma_dummy_rx;
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/* functions to deal with different sized buffers */
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void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
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u32(*get_tx) (struct mpc8xxx_spi *);
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@ -98,6 +164,10 @@ struct mpc8xxx_spi {
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unsigned int flags;
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#define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */
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#define SPI_CPM_MODE (1 << 1) /* CPM/QE ("DMA") mode */
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#define SPI_CPM1 (1 << 2) /* SPI unit is in CPM1 block */
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#define SPI_CPM2 (1 << 3) /* SPI unit is in CPM2 block */
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#define SPI_QE (1 << 4) /* SPI unit is in QE block */
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struct workqueue_struct *workqueue;
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struct work_struct work;
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@ -108,6 +178,10 @@ struct mpc8xxx_spi {
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struct completion done;
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};
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static void *mpc8xxx_dummy_rx;
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static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
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static int mpc8xxx_dummy_rx_refcnt;
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struct spi_mpc8xxx_cs {
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/* functions to deal with different sized buffers */
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void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
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@ -173,6 +247,22 @@ static void mpc8xxx_spi_change_mode(struct spi_device *spi)
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mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
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mpc8xxx_spi_write_reg(mode, cs->hw_mode);
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/* When in CPM mode, we need to reinit tx and rx. */
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if (mspi->flags & SPI_CPM_MODE) {
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if (mspi->flags & SPI_QE) {
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qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
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QE_CR_PROTOCOL_UNSPECIFIED, 0);
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} else {
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cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
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if (mspi->flags & SPI_CPM1) {
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out_be16(&mspi->pram->rbptr,
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in_be16(&mspi->pram->rbase));
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out_be16(&mspi->pram->tbptr,
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in_be16(&mspi->pram->tbase));
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}
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}
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}
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local_irq_restore(flags);
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}
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@ -298,19 +388,133 @@ int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
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return 0;
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}
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static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
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static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
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{
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struct mpc8xxx_spi *mpc8xxx_spi;
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u32 word, len, bits_per_word;
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struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
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struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
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unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
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unsigned int xfer_ofs;
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mpc8xxx_spi = spi_master_get_devdata(spi->master);
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xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
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out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
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out_be16(&rx_bd->cbd_datlen, 0);
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out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
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out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
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out_be16(&tx_bd->cbd_datlen, xfer_len);
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out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
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BD_SC_LAST);
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/* start transfer */
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mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
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}
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static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
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struct spi_transfer *t, bool is_dma_mapped)
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{
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struct device *dev = mspi->dev;
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if (is_dma_mapped) {
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mspi->map_tx_dma = 0;
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mspi->map_rx_dma = 0;
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} else {
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mspi->map_tx_dma = 1;
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mspi->map_rx_dma = 1;
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}
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if (!t->tx_buf) {
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mspi->tx_dma = mspi->dma_dummy_tx;
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mspi->map_tx_dma = 0;
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}
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if (!t->rx_buf) {
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mspi->rx_dma = mspi->dma_dummy_rx;
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mspi->map_rx_dma = 0;
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}
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if (mspi->map_tx_dma) {
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void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
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mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev, mspi->tx_dma)) {
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dev_err(dev, "unable to map tx dma\n");
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return -ENOMEM;
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}
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} else {
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mspi->tx_dma = t->tx_dma;
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}
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if (mspi->map_rx_dma) {
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mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(dev, mspi->rx_dma)) {
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dev_err(dev, "unable to map rx dma\n");
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goto err_rx_dma;
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}
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} else {
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mspi->rx_dma = t->rx_dma;
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}
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/* enable rx ints */
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mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
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mspi->xfer_in_progress = t;
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mspi->count = t->len;
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/* start CPM transfers */
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mpc8xxx_spi_cpm_bufs_start(mspi);
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return 0;
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err_rx_dma:
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if (mspi->map_tx_dma)
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dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
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return -ENOMEM;
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}
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static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
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{
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struct device *dev = mspi->dev;
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struct spi_transfer *t = mspi->xfer_in_progress;
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if (mspi->map_tx_dma)
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dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
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if (mspi->map_tx_dma)
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dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
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mspi->xfer_in_progress = NULL;
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}
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static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
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struct spi_transfer *t, unsigned int len)
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{
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u32 word;
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mspi->count = len;
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/* enable rx ints */
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mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
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/* transmit word */
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word = mspi->get_tx(mspi);
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mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
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return 0;
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}
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static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
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bool is_dma_mapped)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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unsigned int len = t->len;
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u8 bits_per_word;
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int ret;
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mpc8xxx_spi->tx = t->tx_buf;
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mpc8xxx_spi->rx = t->rx_buf;
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bits_per_word = spi->bits_per_word;
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if (t->bits_per_word)
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bits_per_word = t->bits_per_word;
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len = t->len;
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if (bits_per_word > 8) {
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/* invalid length? */
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if (len & 1)
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@ -323,22 +527,27 @@ static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
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return -EINVAL;
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len /= 2;
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}
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mpc8xxx_spi->count = len;
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mpc8xxx_spi->tx = t->tx_buf;
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mpc8xxx_spi->rx = t->rx_buf;
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INIT_COMPLETION(mpc8xxx_spi->done);
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/* enable rx ints */
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mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, SPIM_NE);
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/* transmit word */
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word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
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mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word);
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if (mpc8xxx_spi->flags & SPI_CPM_MODE)
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ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
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else
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ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
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if (ret)
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return ret;
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wait_for_completion(&mpc8xxx_spi->done);
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/* disable rx ints */
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mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
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if (mpc8xxx_spi->flags & SPI_CPM_MODE)
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mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
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return mpc8xxx_spi->count;
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}
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@ -369,7 +578,7 @@ static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
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}
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cs_change = t->cs_change;
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if (t->len)
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status = mpc8xxx_spi_bufs(spi, t);
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status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
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if (status) {
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status = -EMSGSIZE;
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break;
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@ -458,45 +667,80 @@ static int mpc8xxx_spi_setup(struct spi_device *spi)
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return 0;
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}
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static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
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static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = context_data;
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u32 event;
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irqreturn_t ret = IRQ_NONE;
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u16 len;
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/* Get interrupt events(tx/rx) */
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event = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event);
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dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
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in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
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/* We need handle RX first */
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if (event & SPIE_NE) {
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u32 rx_data = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->receive);
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if (mpc8xxx_spi->rx)
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mpc8xxx_spi->get_rx(rx_data, mpc8xxx_spi);
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ret = IRQ_HANDLED;
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}
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if ((event & SPIE_NF) == 0)
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/* spin until TX is done */
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while (((event =
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mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event)) &
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SPIE_NF) == 0)
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cpu_relax();
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mpc8xxx_spi->count -= 1;
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if (mpc8xxx_spi->count) {
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u32 word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
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mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word);
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} else {
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complete(&mpc8xxx_spi->done);
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len = in_be16(&mspi->rx_bd->cbd_datlen);
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if (len > mspi->count) {
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WARN_ON(1);
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len = mspi->count;
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}
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/* Clear the events */
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mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, event);
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mpc8xxx_spi_write_reg(&mspi->base->event, events);
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mspi->count -= len;
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if (mspi->count)
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mpc8xxx_spi_cpm_bufs_start(mspi);
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else
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complete(&mspi->done);
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}
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static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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{
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/* We need handle RX first */
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if (events & SPIE_NE) {
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u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
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if (mspi->rx)
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mspi->get_rx(rx_data, mspi);
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}
|
||||
|
||||
if ((events & SPIE_NF) == 0)
|
||||
/* spin until TX is done */
|
||||
while (((events =
|
||||
mpc8xxx_spi_read_reg(&mspi->base->event)) &
|
||||
SPIE_NF) == 0)
|
||||
cpu_relax();
|
||||
|
||||
/* Clear the events */
|
||||
mpc8xxx_spi_write_reg(&mspi->base->event, events);
|
||||
|
||||
mspi->count -= 1;
|
||||
if (mspi->count) {
|
||||
u32 word = mspi->get_tx(mspi);
|
||||
|
||||
mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
|
||||
} else {
|
||||
complete(&mspi->done);
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
|
||||
{
|
||||
struct mpc8xxx_spi *mspi = context_data;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
u32 events;
|
||||
|
||||
/* Get interrupt events(tx/rx) */
|
||||
events = mpc8xxx_spi_read_reg(&mspi->base->event);
|
||||
if (events)
|
||||
ret = IRQ_HANDLED;
|
||||
|
||||
dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
|
||||
|
||||
if (mspi->flags & SPI_CPM_MODE)
|
||||
mpc8xxx_spi_cpm_irq(mspi, events);
|
||||
else
|
||||
mpc8xxx_spi_cpu_irq(mspi, events);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mpc8xxx_spi_transfer(struct spi_device *spi,
|
||||
struct spi_message *m)
|
||||
{
|
||||
|
|
@ -520,10 +764,212 @@ static void mpc8xxx_spi_cleanup(struct spi_device *spi)
|
|||
kfree(spi->controller_state);
|
||||
}
|
||||
|
||||
static void *mpc8xxx_spi_alloc_dummy_rx(void)
|
||||
{
|
||||
mutex_lock(&mpc8xxx_dummy_rx_lock);
|
||||
|
||||
if (!mpc8xxx_dummy_rx)
|
||||
mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
|
||||
if (mpc8xxx_dummy_rx)
|
||||
mpc8xxx_dummy_rx_refcnt++;
|
||||
|
||||
mutex_unlock(&mpc8xxx_dummy_rx_lock);
|
||||
|
||||
return mpc8xxx_dummy_rx;
|
||||
}
|
||||
|
||||
static void mpc8xxx_spi_free_dummy_rx(void)
|
||||
{
|
||||
mutex_lock(&mpc8xxx_dummy_rx_lock);
|
||||
|
||||
switch (mpc8xxx_dummy_rx_refcnt) {
|
||||
case 0:
|
||||
WARN_ON(1);
|
||||
break;
|
||||
case 1:
|
||||
kfree(mpc8xxx_dummy_rx);
|
||||
mpc8xxx_dummy_rx = NULL;
|
||||
/* fall through */
|
||||
default:
|
||||
mpc8xxx_dummy_rx_refcnt--;
|
||||
break;
|
||||
}
|
||||
|
||||
mutex_unlock(&mpc8xxx_dummy_rx_lock);
|
||||
}
|
||||
|
||||
static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
|
||||
{
|
||||
struct device *dev = mspi->dev;
|
||||
struct device_node *np = dev_archdata_get_node(&dev->archdata);
|
||||
const u32 *iprop;
|
||||
int size;
|
||||
unsigned long spi_base_ofs;
|
||||
unsigned long pram_ofs = -ENOMEM;
|
||||
|
||||
/* Can't use of_address_to_resource(), QE muram isn't at 0. */
|
||||
iprop = of_get_property(np, "reg", &size);
|
||||
|
||||
/* QE with a fixed pram location? */
|
||||
if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
|
||||
return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
|
||||
|
||||
/* QE but with a dynamic pram location? */
|
||||
if (mspi->flags & SPI_QE) {
|
||||
pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
|
||||
qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
|
||||
QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
|
||||
return pram_ofs;
|
||||
}
|
||||
|
||||
/* CPM1 and CPM2 pram must be at a fixed addr. */
|
||||
if (!iprop || size != sizeof(*iprop) * 4)
|
||||
return -ENOMEM;
|
||||
|
||||
spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2);
|
||||
if (IS_ERR_VALUE(spi_base_ofs))
|
||||
return -ENOMEM;
|
||||
|
||||
if (mspi->flags & SPI_CPM2) {
|
||||
pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
|
||||
if (!IS_ERR_VALUE(pram_ofs)) {
|
||||
u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs);
|
||||
|
||||
out_be16(spi_base, pram_ofs);
|
||||
}
|
||||
} else {
|
||||
struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs);
|
||||
u16 rpbase = in_be16(&pram->rpbase);
|
||||
|
||||
/* Microcode relocation patch applied? */
|
||||
if (rpbase)
|
||||
pram_ofs = rpbase;
|
||||
else
|
||||
return spi_base_ofs;
|
||||
}
|
||||
|
||||
cpm_muram_free(spi_base_ofs);
|
||||
return pram_ofs;
|
||||
}
|
||||
|
||||
static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
|
||||
{
|
||||
struct device *dev = mspi->dev;
|
||||
struct device_node *np = dev_archdata_get_node(&dev->archdata);
|
||||
const u32 *iprop;
|
||||
int size;
|
||||
unsigned long pram_ofs;
|
||||
unsigned long bds_ofs;
|
||||
|
||||
if (!(mspi->flags & SPI_CPM_MODE))
|
||||
return 0;
|
||||
|
||||
if (!mpc8xxx_spi_alloc_dummy_rx())
|
||||
return -ENOMEM;
|
||||
|
||||
if (mspi->flags & SPI_QE) {
|
||||
iprop = of_get_property(np, "cell-index", &size);
|
||||
if (iprop && size == sizeof(*iprop))
|
||||
mspi->subblock = *iprop;
|
||||
|
||||
switch (mspi->subblock) {
|
||||
default:
|
||||
dev_warn(dev, "cell-index unspecified, assuming SPI1");
|
||||
/* fall through */
|
||||
case 0:
|
||||
mspi->subblock = QE_CR_SUBBLOCK_SPI1;
|
||||
break;
|
||||
case 1:
|
||||
mspi->subblock = QE_CR_SUBBLOCK_SPI2;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
|
||||
if (IS_ERR_VALUE(pram_ofs)) {
|
||||
dev_err(dev, "can't allocate spi parameter ram\n");
|
||||
goto err_pram;
|
||||
}
|
||||
|
||||
bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
|
||||
sizeof(*mspi->rx_bd), 8);
|
||||
if (IS_ERR_VALUE(bds_ofs)) {
|
||||
dev_err(dev, "can't allocate bds\n");
|
||||
goto err_bds;
|
||||
}
|
||||
|
||||
mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
|
||||
DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
|
||||
dev_err(dev, "unable to map dummy tx buffer\n");
|
||||
goto err_dummy_tx;
|
||||
}
|
||||
|
||||
mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
|
||||
DMA_FROM_DEVICE);
|
||||
if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
|
||||
dev_err(dev, "unable to map dummy rx buffer\n");
|
||||
goto err_dummy_rx;
|
||||
}
|
||||
|
||||
mspi->pram = cpm_muram_addr(pram_ofs);
|
||||
|
||||
mspi->tx_bd = cpm_muram_addr(bds_ofs);
|
||||
mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
|
||||
|
||||
/* Initialize parameter ram. */
|
||||
out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
|
||||
out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
|
||||
out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
|
||||
out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
|
||||
out_be16(&mspi->pram->mrblr, SPI_MRBLR);
|
||||
out_be32(&mspi->pram->rstate, 0);
|
||||
out_be32(&mspi->pram->rdp, 0);
|
||||
out_be16(&mspi->pram->rbptr, 0);
|
||||
out_be16(&mspi->pram->rbc, 0);
|
||||
out_be32(&mspi->pram->rxtmp, 0);
|
||||
out_be32(&mspi->pram->tstate, 0);
|
||||
out_be32(&mspi->pram->tdp, 0);
|
||||
out_be16(&mspi->pram->tbptr, 0);
|
||||
out_be16(&mspi->pram->tbc, 0);
|
||||
out_be32(&mspi->pram->txtmp, 0);
|
||||
|
||||
return 0;
|
||||
|
||||
err_dummy_rx:
|
||||
dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
|
||||
err_dummy_tx:
|
||||
cpm_muram_free(bds_ofs);
|
||||
err_bds:
|
||||
cpm_muram_free(pram_ofs);
|
||||
err_pram:
|
||||
mpc8xxx_spi_free_dummy_rx();
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
|
||||
{
|
||||
struct device *dev = mspi->dev;
|
||||
|
||||
dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
|
||||
dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
|
||||
cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
|
||||
cpm_muram_free(cpm_muram_offset(mspi->pram));
|
||||
mpc8xxx_spi_free_dummy_rx();
|
||||
}
|
||||
|
||||
static const char *mpc8xxx_spi_strmode(unsigned int flags)
|
||||
{
|
||||
if (flags & SPI_QE_CPU_MODE)
|
||||
if (flags & SPI_QE_CPU_MODE) {
|
||||
return "QE CPU";
|
||||
} else if (flags & SPI_CPM_MODE) {
|
||||
if (flags & SPI_QE)
|
||||
return "QE";
|
||||
else if (flags & SPI_CPM2)
|
||||
return "CPM2";
|
||||
else
|
||||
return "CPM1";
|
||||
}
|
||||
return "CPU";
|
||||
}
|
||||
|
||||
|
|
@ -553,11 +999,16 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
|
|||
master->cleanup = mpc8xxx_spi_cleanup;
|
||||
|
||||
mpc8xxx_spi = spi_master_get_devdata(master);
|
||||
mpc8xxx_spi->dev = dev;
|
||||
mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
|
||||
mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
|
||||
mpc8xxx_spi->flags = pdata->flags;
|
||||
mpc8xxx_spi->spibrg = pdata->sysclk;
|
||||
|
||||
ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
|
||||
if (ret)
|
||||
goto err_cpm_init;
|
||||
|
||||
mpc8xxx_spi->rx_shift = 0;
|
||||
mpc8xxx_spi->tx_shift = 0;
|
||||
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
|
||||
|
|
@ -570,7 +1021,7 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
|
|||
mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
|
||||
if (mpc8xxx_spi->base == NULL) {
|
||||
ret = -ENOMEM;
|
||||
goto put_master;
|
||||
goto err_ioremap;
|
||||
}
|
||||
|
||||
mpc8xxx_spi->irq = irq;
|
||||
|
|
@ -624,7 +1075,9 @@ free_irq:
|
|||
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
|
||||
unmap_io:
|
||||
iounmap(mpc8xxx_spi->base);
|
||||
put_master:
|
||||
err_ioremap:
|
||||
mpc8xxx_spi_cpm_free(mpc8xxx_spi);
|
||||
err_cpm_init:
|
||||
spi_master_put(master);
|
||||
err:
|
||||
return ERR_PTR(ret);
|
||||
|
|
@ -644,6 +1097,7 @@ static int __devexit mpc8xxx_spi_remove(struct device *dev)
|
|||
|
||||
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
|
||||
iounmap(mpc8xxx_spi->base);
|
||||
mpc8xxx_spi_cpm_free(mpc8xxx_spi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -806,6 +1260,12 @@ static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
|
|||
prop = of_get_property(np, "mode", NULL);
|
||||
if (prop && !strcmp(prop, "cpu-qe"))
|
||||
pdata->flags = SPI_QE_CPU_MODE;
|
||||
else if (prop && !strcmp(prop, "qe"))
|
||||
pdata->flags = SPI_CPM_MODE | SPI_QE;
|
||||
else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
|
||||
pdata->flags = SPI_CPM_MODE | SPI_CPM2;
|
||||
else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
|
||||
pdata->flags = SPI_CPM_MODE | SPI_CPM1;
|
||||
|
||||
ret = of_mpc8xxx_spi_get_chipselects(dev);
|
||||
if (ret)
|
||||
|
|
|
|||
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