Few fixes for omap clocks, PRM and hwmod code:
- Fix bogus comparison of struct clk pointers, turns out we can fix it by just removing the comparison - Fix am437 hardreset implementation and remove boottime warnings by adding the VPFE hwmod data - Regression fix for am43xx PRM code, simplify things by reusing the omap4 PRM implementation -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVURcqAAoJEBvUPslcq6Vz8tgP/RlnR65BdDB+l1157Q3wptt1 PuuloT7lVBz3rHTiCK8KcHlk/pvZHW/I5eRVrWrEYPaFW5szwLSZxOOzGpld8Ues PuCDdktBPwdSuqFKDmyl/SusRyKvqWFJn6KnzO1Nwz6I9NhAhox9JOi7TCYw7s9A ZPYjZATfdIBFmNDkBjgRusI7s/Zt5JwT7/Uc0qtAPJ+fyh9BvuF69kN9cR+yAXt8 ArvDeG7B7/6kttAs6yejVK7Ae9hOspEPeDHEc8rb63fK3zr0gzptejB1CYvvAWuB eXkuc1ExFUff7/nEivXQ2oApuaAuHMjtqmZgsDB4aj8Ks/PHi5tvDFqB4s2RCdf3 PB4yD6hzY0/WEPnPM4uXB0PVMdcPINqLT/Gauwr0hRAyEL5Y0Tk0arDyJIgIqY/I AtAIaOaBh/cpOI3YnOal8FJvUvxnPLXxx9cuR+l6cPCBQ3yOgsUF+LtVJBUK/p67 l5ePV/hlEOrQ1FwA+00Wx3f/DmuLt9SAnRMr0xCKZHaIqEM0HzsOYLRt2BcqsiPT oqnRNs7Joik/GIAc0/SGmk26dBCggQldSwRwfKdmgFQcqSwsXsm/QiddE2Gqg3Af TpShZYEGxAp5AyU3FqXlvmMrRJx97vwN1VJltqsDE2GyXM03oK6pkcvUORF3XvrV 1y1RQfrOdqJQZ3JLvsIq =8Ieb -----END PGP SIGNATURE----- Merge tag 'omap-for-v4.1/fixes-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes Merge "Few fixes for omap clocks, PRM and hwmod code" from Tony Lindgren: - Fix bogus comparison of struct clk pointers, turns out we can fix it by just removing the comparison - Fix am437 hardreset implementation and remove boottime warnings by adding the VPFE hwmod data - Regression fix for am43xx PRM code, simplify things by reusing the omap4 PRM implementation * tag 'omap-for-v4.1/fixes-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Remove bogus struct clk comparison for timer clock ARM: AM33xx+: hwmod: re-use omap4 implementations for reset functionality ARM: OMAP4+: PRM: add support for passing status register/bit info to reset ARM: AM43xx: hwmod: add VPFE hwmod entries
This commit is contained in:
Коммит
4c4945392d
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@ -171,6 +171,12 @@
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*/
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#define LINKS_PER_OCP_IF 2
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/*
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* Address offset (in bytes) between the reset control and the reset
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* status registers: 4 bytes on OMAP4
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*/
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#define OMAP4_RST_CTRL_ST_OFFSET 4
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/**
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* struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
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* @enable_module: function to enable a module (via MODULEMODE)
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@ -3016,10 +3022,12 @@ static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
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if (ohri->st_shift)
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pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
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oh->name, ohri->name);
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return omap_prm_deassert_hardreset(ohri->rst_shift, 0,
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return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift,
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oh->clkdm->pwrdm.ptr->prcm_partition,
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oh->clkdm->pwrdm.ptr->prcm_offs,
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oh->prcm.omap4.rstctrl_offs, 0);
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oh->prcm.omap4.rstctrl_offs,
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oh->prcm.omap4.rstctrl_offs +
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OMAP4_RST_CTRL_ST_OFFSET);
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}
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/**
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@ -3047,27 +3055,6 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
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oh->prcm.omap4.rstctrl_offs);
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}
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/**
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* _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args
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* @oh: struct omap_hwmod * to assert hardreset
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* @ohri: hardreset line data
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*
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* Call am33xx_prminst_assert_hardreset() with parameters extracted
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* from the hwmod @oh and the hardreset line data @ohri. Only
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* intended for use as an soc_ops function pointer. Passes along the
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* return value from am33xx_prminst_assert_hardreset(). XXX This
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* function is scheduled for removal when the PRM code is moved into
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* drivers/.
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*/
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static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
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struct omap_hwmod_rst_info *ohri)
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{
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return omap_prm_assert_hardreset(ohri->rst_shift, 0,
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oh->clkdm->pwrdm.ptr->prcm_offs,
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oh->prcm.omap4.rstctrl_offs);
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}
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/**
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* _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args
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* @oh: struct omap_hwmod * to deassert hardreset
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@ -3083,32 +3070,13 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
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static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
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struct omap_hwmod_rst_info *ohri)
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{
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return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0,
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return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift,
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oh->clkdm->pwrdm.ptr->prcm_partition,
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oh->clkdm->pwrdm.ptr->prcm_offs,
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oh->prcm.omap4.rstctrl_offs,
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oh->prcm.omap4.rstst_offs);
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}
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/**
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* _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args
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* @oh: struct omap_hwmod * to test hardreset
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* @ohri: hardreset line data
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*
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* Call am33xx_prminst_is_hardreset_asserted() with parameters
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* extracted from the hwmod @oh and the hardreset line data @ohri.
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* Only intended for use as an soc_ops function pointer. Passes along
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* the return value from am33xx_prminst_is_hardreset_asserted(). XXX
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* This function is scheduled for removal when the PRM code is moved
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* into drivers/.
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*/
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static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
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struct omap_hwmod_rst_info *ohri)
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{
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return omap_prm_is_hardreset_asserted(ohri->rst_shift, 0,
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oh->clkdm->pwrdm.ptr->prcm_offs,
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oh->prcm.omap4.rstctrl_offs);
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}
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/* Public functions */
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u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
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@ -3908,21 +3876,13 @@ void __init omap_hwmod_init(void)
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soc_ops.init_clkdm = _init_clkdm;
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soc_ops.update_context_lost = _omap4_update_context_lost;
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soc_ops.get_context_lost = _omap4_get_context_lost;
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} else if (soc_is_am43xx()) {
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} else if (cpu_is_ti816x() || soc_is_am33xx() || soc_is_am43xx()) {
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soc_ops.enable_module = _omap4_enable_module;
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soc_ops.disable_module = _omap4_disable_module;
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soc_ops.wait_target_ready = _omap4_wait_target_ready;
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soc_ops.assert_hardreset = _omap4_assert_hardreset;
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soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
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soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
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soc_ops.init_clkdm = _init_clkdm;
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} else if (cpu_is_ti816x() || soc_is_am33xx()) {
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soc_ops.enable_module = _omap4_enable_module;
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soc_ops.disable_module = _omap4_disable_module;
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soc_ops.wait_target_ready = _omap4_wait_target_ready;
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soc_ops.assert_hardreset = _am33xx_assert_hardreset;
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soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
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soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
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soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
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soc_ops.init_clkdm = _init_clkdm;
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} else {
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WARN(1, "omap_hwmod: unknown SoC type\n");
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@ -544,6 +544,44 @@ static struct omap_hwmod am43xx_hdq1w_hwmod = {
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},
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};
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static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x104,
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.sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
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.name = "vpfe",
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.sysc = &am43xx_vpfe_sysc,
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};
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static struct omap_hwmod am43xx_vpfe0_hwmod = {
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.name = "vpfe0",
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.class = &am43xx_vpfe_hwmod_class,
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.clkdm_name = "l3s_clkdm",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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.clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
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},
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},
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};
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static struct omap_hwmod am43xx_vpfe1_hwmod = {
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.name = "vpfe1",
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.class = &am43xx_vpfe_hwmod_class,
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.clkdm_name = "l3s_clkdm",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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.clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
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},
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},
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};
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/* Interfaces */
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static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
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.master = &am33xx_l3_main_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
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.master = &am43xx_vpfe0_hwmod,
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.slave = &am33xx_l3_main_hwmod,
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.clk = "l3_gclk",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
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.master = &am43xx_vpfe1_hwmod,
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.slave = &am33xx_l3_main_hwmod,
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.clk = "l3_gclk",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
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.master = &am33xx_l4_ls_hwmod,
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.slave = &am43xx_vpfe0_hwmod,
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.clk = "l4ls_gclk",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
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.master = &am33xx_l4_ls_hwmod,
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.slave = &am43xx_vpfe1_hwmod,
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.clk = "l4ls_gclk",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
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&am33xx_l4_wkup__synctimer,
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&am43xx_l4_ls__timer8,
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&am43xx_l4_ls__dss_dispc,
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&am43xx_l4_ls__dss_rfbi,
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&am43xx_l4_ls__hdq1w,
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&am43xx_l3__vpfe0,
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&am43xx_l3__vpfe1,
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&am43xx_l4_ls__vpfe0,
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&am43xx_l4_ls__vpfe1,
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NULL,
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};
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@ -144,5 +144,6 @@
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#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0
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#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20
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#define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0
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#define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET 0x0068
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#define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET 0x0070
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#endif
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@ -87,12 +87,6 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
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return v;
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}
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/*
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* Address offset (in bytes) between the reset control and the reset
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* status registers: 4 bytes on OMAP4
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*/
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#define OMAP4_RST_CTRL_ST_OFFSET 4
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/**
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* omap4_prminst_is_hardreset_asserted - read the HW reset line state of
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* submodules contained in the hwmod module
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* omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
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* wait
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* @shift: register bit shift corresponding to the reset line to deassert
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* @st_shift: status bit offset, not used for OMAP4+
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* @st_shift: status bit offset corresponding to the reset line
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* @part: PRM partition
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* @inst: PRM instance offset
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* @rstctrl_offs: reset register offset
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* @st_offs: reset status register offset, not used for OMAP4+
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* @rstst_offs: reset status register offset
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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@ -157,11 +151,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
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* of reset, or -EBUSY if the submodule did not exit reset promptly.
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*/
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int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
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u16 rstctrl_offs, u16 st_offs)
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u16 rstctrl_offs, u16 rstst_offs)
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{
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int c;
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u32 mask = 1 << shift;
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u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
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u32 st_mask = 1 << st_shift;
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/* Check the current status to avoid de-asserting the line twice */
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if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
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@ -169,13 +163,13 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
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return -EEXIST;
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/* Clear the reset status by writing 1 to the status bit */
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omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
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omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
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rstst_offs);
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/* de-assert the reset control line */
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omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
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/* wait the status to be set */
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omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
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rstst_offs),
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omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
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inst, rstst_offs),
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MAX_MODULE_HARDRESET_WAIT, c);
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return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
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@ -298,14 +298,11 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
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if (IS_ERR(src))
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return PTR_ERR(src);
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if (clk_get_parent(timer->fclk) != src) {
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r = clk_set_parent(timer->fclk, src);
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if (r < 0) {
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pr_warn("%s: %s cannot set source\n", __func__,
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oh->name);
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clk_put(src);
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return r;
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}
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r = clk_set_parent(timer->fclk, src);
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if (r < 0) {
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pr_warn("%s: %s cannot set source\n", __func__, oh->name);
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clk_put(src);
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return r;
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}
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clk_put(src);
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