sh: pci: Split out new-style PCI core.
This splits off a 'pci-new.c' which is aimed at gradually replacing the pci-auto backend and the arch/sh/drivers/pci/pci.c core respectively. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
Родитель
9ade1217c9
Коммит
4c5107e445
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@ -18,10 +18,17 @@ config SH_PCIDMA_NONCOHERENT
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bridge integrated with your SH CPU, refer carefully to the chip specs
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to see if you can say 'N' here. Otherwise, leave it as 'Y'.
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# Temporary config option for transitioning off of PCI_AUTO
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config PCI_NEW
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bool
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depends on PCI
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default y if CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7780 || \
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CPU_SUBTYPE_SH7785
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# This is also board-specific
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config PCI_AUTO
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bool
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depends on PCI
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depends on PCI && !PCI_NEW
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default y
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config PCI_AUTO_UPDATE_RESOURCES
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@ -34,4 +41,3 @@ config PCI_AUTO_UPDATE_RESOURCES
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for some reason, you have a board that simply refuses to work
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with its resources updated beyond what they are when the device
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is powered up, set this to N. Everyone else will want this as Y.
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@ -2,8 +2,8 @@
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# Makefile for the PCI specific kernel interface routines under Linux.
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#
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obj-y += pci.o
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obj-$(CONFIG_PCI_AUTO) += pci-auto.o
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obj-$(CONFIG_PCI_AUTO) := pci.o pci-auto.o
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obj-$(CONFIG_PCI_NEW) := pci-new.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
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@ -0,0 +1,248 @@
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/*
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* New-style PCI core.
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*
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* Copyright (c) 2002 M. R. Brown
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* Copyright (c) 2004 - 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/dma-debug.h>
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#include <linux/io.h>
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static int __init pcibios_init(void)
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{
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struct pci_channel *p;
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struct pci_bus *bus;
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int busno;
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/* init channels */
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busno = 0;
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for (p = board_pci_channels; p->init; p++) {
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if (p->init(p) == 0)
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p->enabled = 1;
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else
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pr_err("Unable to init pci channel %d\n", busno);
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busno++;
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}
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/* scan the buses */
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busno = 0;
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for (p = board_pci_channels; p->init; p++) {
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if (p->enabled) {
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bus = pci_scan_bus(busno, p->pci_ops, p);
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busno = bus->subordinate + 1;
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pci_bus_size_bridges(bus);
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pci_bus_assign_resources(bus);
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pci_enable_bridges(bus);
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}
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}
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pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);
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dma_debug_add_bus(&pci_bus_type);
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return 0;
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}
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subsys_initcall(pcibios_init);
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static void pcibios_fixup_device_resources(struct pci_dev *dev,
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struct pci_bus *bus)
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{
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/* Update device resources. */
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struct pci_channel *chan = bus->sysdata;
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unsigned long offset = 0;
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int i;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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if (!dev->resource[i].start)
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continue;
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if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
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continue;
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if (dev->resource[i].flags & IORESOURCE_IO)
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offset = chan->io_base;
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else if (dev->resource[i].flags & IORESOURCE_MEM)
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offset = 0;
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dev->resource[i].start += offset;
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dev->resource[i].end += offset;
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}
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}
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/*
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* Called after each bus is probed, but before its children
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* are examined.
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*/
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void __devinit __weak pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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struct list_head *ln;
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struct pci_channel *chan = bus->sysdata;
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if (!dev) {
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bus->resource[0] = chan->io_resource;
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bus->resource[1] = chan->mem_resource;
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}
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for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
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dev = pci_dev_b(ln);
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if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
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pcibios_fixup_device_resources(dev, bus);
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}
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}
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void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res)
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{
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struct pci_channel *chan = dev->sysdata;
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO)
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offset = chan->io_base;
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else if (res->flags & IORESOURCE_MEM)
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offset = 0;
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region->start = res->start - offset;
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region->end = res->end - offset;
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}
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void __devinit
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pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region)
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{
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struct pci_channel *chan = dev->sysdata;
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO)
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offset = chan->io_base;
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else if (res->flags & IORESOURCE_MEM)
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offset = 0;
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res->start = region->start + offset;
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res->end = region->end + offset;
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}
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void pcibios_align_resource(void *data, struct resource *res,
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resource_size_t size, resource_size_t align)
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__attribute__ ((weak));
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*/
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void pcibios_align_resource(void *data, struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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if (res->flags & IORESOURCE_IO) {
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resource_size_t start = res->start;
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if (start & 0x300) {
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start = (start + 0x3ff) & ~0x3ff;
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res->start = start;
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}
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}
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int idx;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for(idx=0; idx<6; idx++) {
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if (!(mask & (1 << idx)))
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continue;
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r = &dev->resource[idx];
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if (!r->start && r->end) {
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printk(KERN_ERR "PCI: Device %s not available because "
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"of resource collisions\n", pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (dev->resource[PCI_ROM_RESOURCE].start)
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cmd |= PCI_COMMAND_MEMORY;
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if (cmd != old_cmd) {
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printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
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pci_name(dev), old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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/*
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* If we set up a device for bus mastering, we need to check and set
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* the latency timer as it may not be properly set.
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*/
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static unsigned int pcibios_max_latency = 255;
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat < 16)
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lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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else if (lat > pcibios_max_latency)
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lat = pcibios_max_latency;
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else
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return;
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printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
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pci_name(dev), lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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void __init pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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resource_size_t start = pci_resource_start(dev, bar);
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resource_size_t len = pci_resource_len(dev, bar);
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unsigned long flags = pci_resource_flags(dev, bar);
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if (unlikely(!len || !start))
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return NULL;
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if (maxlen && len > maxlen)
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len = maxlen;
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/*
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* Presently the IORESOURCE_MEM case is a bit special, most
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* SH7751 style PCI controllers have PCI memory at a fixed
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* location in the address space where no remapping is desired.
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* With the IORESOURCE_MEM case more care has to be taken
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* to inhibit page table mapping for legacy cores, but this is
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* punted off to __ioremap().
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* -- PFM.
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*/
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if (flags & IORESOURCE_IO)
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return ioport_map(start, len);
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if (flags & IORESOURCE_MEM)
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return ioremap(start, len);
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return NULL;
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}
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EXPORT_SYMBOL(pci_iomap);
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void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
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{
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iounmap(addr);
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}
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EXPORT_SYMBOL(pci_iounmap);
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EXPORT_SYMBOL(board_pci_channels);
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