cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
Currently Exynos cpufreq drivers rely on globally mapped clock controller registers to configure frequency of CPU cores. This is obviously wrong and will be removed in near future, but to enable support for multi-platform builds without introducing a regression it needs to be worked around. This patch hacks the code to look for clock controller node in device tree and map its registers using of_iomap(), instead of relying on global mapping, so dependencies on platform headers are removed and the driver can compile again with multiplatform support. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Tomasz Figa
Kukjin Kim
Родитель
9dfa92ec40
Коммит
4c8d819343
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@ -30,7 +30,7 @@ config ARM_EXYNOS_CPUFREQ
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config ARM_EXYNOS4210_CPUFREQ
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bool "SAMSUNG EXYNOS4210"
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depends on CPU_EXYNOS4210 && !ARCH_MULTIPLATFORM
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depends on CPU_EXYNOS4210
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default y
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select ARM_EXYNOS_CPUFREQ
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help
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@ -41,7 +41,7 @@ config ARM_EXYNOS4210_CPUFREQ
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config ARM_EXYNOS4X12_CPUFREQ
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bool "SAMSUNG EXYNOS4x12"
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depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
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depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
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default y
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select ARM_EXYNOS_CPUFREQ
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help
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@ -52,7 +52,7 @@ config ARM_EXYNOS4X12_CPUFREQ
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config ARM_EXYNOS5250_CPUFREQ
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bool "SAMSUNG EXYNOS5250"
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depends on SOC_EXYNOS5250 && !ARCH_MULTIPLATFORM
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depends on SOC_EXYNOS5250
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default y
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select ARM_EXYNOS_CPUFREQ
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help
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@ -19,8 +19,6 @@
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <plat/cpu.h>
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#include "exynos-cpufreq.h"
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static struct exynos_dvfs_info *exynos_info;
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@ -49,6 +49,7 @@ struct exynos_dvfs_info {
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struct cpufreq_frequency_table *freq_table;
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void (*set_freq)(unsigned int, unsigned int);
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bool (*need_apll_change)(unsigned int, unsigned int);
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void __iomem *cmu_regs;
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};
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#ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ
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@ -76,24 +77,21 @@ static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
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}
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#endif
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#include <plat/cpu.h>
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#include <mach/map.h>
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#define EXYNOS4_CLKSRC_CPU 0x14200
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#define EXYNOS4_CLKMUX_STATCPU 0x14400
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#define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU + 0x14200)
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#define EXYNOS4_CLKMUX_STATCPU (S5P_VA_CMU + 0x14400)
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#define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU + 0x14500)
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#define EXYNOS4_CLKDIV_CPU1 (S5P_VA_CMU + 0x14504)
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#define EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU + 0x14600)
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#define EXYNOS4_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x14604)
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#define EXYNOS4_CLKDIV_CPU 0x14500
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#define EXYNOS4_CLKDIV_CPU1 0x14504
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#define EXYNOS4_CLKDIV_STATCPU 0x14600
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#define EXYNOS4_CLKDIV_STATCPU1 0x14604
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#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
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#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
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#define EXYNOS5_APLL_LOCK (S5P_VA_CMU + 0x00000)
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#define EXYNOS5_APLL_CON0 (S5P_VA_CMU + 0x00100)
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#define EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU + 0x00400)
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#define EXYNOS5_CLKDIV_CPU0 (S5P_VA_CMU + 0x00500)
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#define EXYNOS5_CLKDIV_CPU1 (S5P_VA_CMU + 0x00504)
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#define EXYNOS5_CLKDIV_STATCPU0 (S5P_VA_CMU + 0x00600)
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#define EXYNOS5_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x00604)
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#define EXYNOS5_APLL_LOCK 0x00000
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#define EXYNOS5_APLL_CON0 0x00100
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#define EXYNOS5_CLKMUX_STATCPU 0x00400
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#define EXYNOS5_CLKDIV_CPU0 0x00500
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#define EXYNOS5_CLKDIV_CPU1 0x00504
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#define EXYNOS5_CLKDIV_STATCPU0 0x00600
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#define EXYNOS5_CLKDIV_STATCPU1 0x00604
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@ -16,6 +16,8 @@
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "exynos-cpufreq.h"
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@ -23,6 +25,7 @@ static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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static struct exynos_dvfs_info *cpufreq;
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static unsigned int exynos4210_volt_table[] = {
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1250000, 1150000, 1050000, 975000, 950000,
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@ -60,20 +63,20 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
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tmp = apll_freq_4210[div_index].clk_div_cpu0;
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
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__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
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do {
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tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
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tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU);
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} while (tmp & 0x1111111);
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/* Change Divider - CPU1 */
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tmp = apll_freq_4210[div_index].clk_div_cpu1;
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
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__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
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do {
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tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
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tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
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} while (tmp & 0x11);
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}
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@ -85,7 +88,7 @@ static void exynos4210_set_apll(unsigned int index)
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clk_set_parent(moutcore, mout_mpll);
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do {
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tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
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tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
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>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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@ -96,7 +99,7 @@ static void exynos4210_set_apll(unsigned int index)
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clk_set_parent(moutcore, mout_apll);
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do {
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tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
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tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
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tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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@ -115,8 +118,30 @@ static void exynos4210_set_frequency(unsigned int old_index,
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int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
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{
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struct device_node *np;
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unsigned long rate;
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/*
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* HACK: This is a temporary workaround to get access to clock
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* controller registers directly and remove static mappings and
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* dependencies on platform headers. It is necessary to enable
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* Exynos multi-platform support and will be removed together with
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* this whole driver as soon as Exynos gets migrated to use
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* cpufreq-cpu0 driver.
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*/
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-clock");
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if (!np) {
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pr_err("%s: failed to find clock controller DT node\n",
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__func__);
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return -ENODEV;
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}
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info->cmu_regs = of_iomap(np, 0);
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if (!info->cmu_regs) {
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pr_err("%s: failed to map CMU registers\n", __func__);
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return -EFAULT;
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}
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cpu_clk = clk_get(NULL, "armclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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@ -143,6 +168,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
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info->freq_table = exynos4210_freq_table;
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info->set_freq = exynos4210_set_frequency;
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cpufreq = info;
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return 0;
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err_mout_apll:
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@ -16,6 +16,8 @@
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "exynos-cpufreq.h"
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@ -23,6 +25,7 @@ static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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static struct exynos_dvfs_info *cpufreq;
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static unsigned int exynos4x12_volt_table[] = {
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1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
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@ -105,19 +108,20 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
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tmp = apll_freq_4x12[div_index].clk_div_cpu0;
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
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__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
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while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
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while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU)
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& 0x11111111)
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cpu_relax();
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/* Change Divider - CPU1 */
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tmp = apll_freq_4x12[div_index].clk_div_cpu1;
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
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__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
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do {
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cpu_relax();
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tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
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tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
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} while (tmp != 0x0);
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}
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@ -130,7 +134,7 @@ static void exynos4x12_set_apll(unsigned int index)
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do {
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cpu_relax();
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tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
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tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
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>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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@ -142,7 +146,7 @@ static void exynos4x12_set_apll(unsigned int index)
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do {
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cpu_relax();
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tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
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tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
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tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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@ -161,8 +165,30 @@ static void exynos4x12_set_frequency(unsigned int old_index,
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int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
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{
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struct device_node *np;
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unsigned long rate;
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/*
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* HACK: This is a temporary workaround to get access to clock
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* controller registers directly and remove static mappings and
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* dependencies on platform headers. It is necessary to enable
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* Exynos multi-platform support and will be removed together with
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* this whole driver as soon as Exynos gets migrated to use
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* cpufreq-cpu0 driver.
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*/
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
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if (!np) {
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pr_err("%s: failed to find clock controller DT node\n",
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__func__);
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return -ENODEV;
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}
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info->cmu_regs = of_iomap(np, 0);
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if (!info->cmu_regs) {
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pr_err("%s: failed to map CMU registers\n", __func__);
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return -EFAULT;
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}
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cpu_clk = clk_get(NULL, "armclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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@ -194,6 +220,8 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
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info->freq_table = exynos4x12_freq_table;
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info->set_freq = exynos4x12_set_frequency;
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cpufreq = info;
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return 0;
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err_mout_apll:
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@ -16,8 +16,8 @@
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <mach/map.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "exynos-cpufreq.h"
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@ -25,6 +25,7 @@ static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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static struct exynos_dvfs_info *cpufreq;
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static unsigned int exynos5250_volt_table[] = {
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1300000, 1250000, 1225000, 1200000, 1150000,
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@ -87,17 +88,18 @@ static void set_clkdiv(unsigned int div_index)
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tmp = apll_freq_5250[div_index].clk_div_cpu0;
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__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
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__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0);
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while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
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while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0)
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& 0x11111111)
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cpu_relax();
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/* Change Divider - CPU1 */
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tmp = apll_freq_5250[div_index].clk_div_cpu1;
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__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
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__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1);
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while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
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while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11)
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cpu_relax();
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}
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@ -111,7 +113,8 @@ static void set_apll(unsigned int index)
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do {
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cpu_relax();
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tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
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tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU)
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>> 16);
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tmp &= 0x7;
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} while (tmp != 0x2);
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@ -122,7 +125,7 @@ static void set_apll(unsigned int index)
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do {
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cpu_relax();
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tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
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tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU);
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tmp &= (0x7 << 16);
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} while (tmp != (0x1 << 16));
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}
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@ -141,8 +144,30 @@ static void exynos5250_set_frequency(unsigned int old_index,
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int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
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{
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struct device_node *np;
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unsigned long rate;
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/*
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* HACK: This is a temporary workaround to get access to clock
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* controller registers directly and remove static mappings and
|
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* dependencies on platform headers. It is necessary to enable
|
||||
* Exynos multi-platform support and will be removed together with
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* this whole driver as soon as Exynos gets migrated to use
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* cpufreq-cpu0 driver.
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*/
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-clock");
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if (!np) {
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pr_err("%s: failed to find clock controller DT node\n",
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__func__);
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return -ENODEV;
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}
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info->cmu_regs = of_iomap(np, 0);
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if (!info->cmu_regs) {
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pr_err("%s: failed to map CMU registers\n", __func__);
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return -EFAULT;
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}
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cpu_clk = clk_get(NULL, "armclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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@ -169,6 +194,8 @@ int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
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info->freq_table = exynos5250_freq_table;
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info->set_freq = exynos5250_set_frequency;
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cpufreq = info;
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return 0;
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err_mout_apll:
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